Pinfield with ground vias adjacent to an auxiliary signal conductor for crosstalk mitigation

Patent metadata

Field	Value
Publication number	US-11569617-B2
Application number	US-202016949194-A
Country	US
Kind code	B2
Filing date	Oct 19, 2020
Priority date	Aug 13, 2015
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

A system board is provided that includes a connector. The connector includes a pinfield. The pinfield includes a set of differential signal conductors to correspond to pins of a set of differential signaling pairs; a set of one or more auxiliary signal conductors to carry auxiliary signals; and a plurality of thru-hole ground vias adjacent to a particular one of the auxiliary signal conductors in the set of auxiliary signal conductors.

First claim

What is claimed is:

1. An apparatus comprising:
a system board comprising:
a pinfield, wherein the pinfield comprises:
a set of differential signal conductors to correspond to pins of a connector for a set of differential signaling pairs;
a set of ground conductors to correspond to pins of the connector for a set of grounds;
a set of sideband signal conductors to carry sideband signals; and
a plurality of sentry ground vias adjacent to a particular one of the sideband signal conductors in the set of sideband signal conductors;

wherein the plurality of sentry ground vias have a diameter smaller than diameters of pins of the connector and smaller than diameters of vias of the sideband signal conductors.

2. The apparatus of claim 1 , wherein the plurality of sentry ground vias comprises at least three sentry ground vias adjacent to a particular one of the sideband signal conductors in the set of sideband signal conductors.

3. The apparatus of claim 1 , wherein the plurality of sentry ground vias comprises a plurality of thru-hole vias.

4. The apparatus of claim 1 , further comprising a thru-hole connector joined to the pinfield.

5. The apparatus of claim 4 , wherein the connector comprises one of an x1, x4, x8, or x16 width connector.

6. The apparatus of claim 1 , wherein the set of sideband signal conductors comprises one or more of a conductor for a clock request (CLKREQ) signal, a conductor for a reference clock (REFCLK) signal, or a conductor for a present (PRSNT) signal.

7. The apparatus of claim 1 , wherein the one or more sideband signal conductors comprises a conductor for a power break (PWRBRK) signal.

8. The apparatus of claim 1 , wherein one of the sideband signals comprise active low signals.

9. The apparatus of claim 1 , wherein the pinfield is based on a Peripheral Component Interconnect Express (PCIe) protocol.

10. The apparatus of claim 1 , wherein the pinfield is based on an interconnect other than a PCIe-based interconnect.

11. The apparatus of claim 1 , wherein the set of sideband signal conductors comprises sideband signal conductors in a range from A 12 /B 12 to A 82 /B 82 .

12. A computing device comprising:
a pinfield compliant with a PCIe-based specification, wherein the pinfield comprises:
a set of differential signal conductors to carry differential signals to transmit and receive data on an interface compliant with the PCIe-based specification, wherein the set of different signal conductors correspond to pins of a connector;
a set of ground conductors to correspond to ground pins of the connector;
a set of sideband signal vias to carry one or more of clock signals and sideband signals; and
a set of sentry ground vias adjacent to each one of the sideband signal vias in the set of sideband signal vias;

wherein the set of sentry ground vias have a diameter smaller than pins of the connector and smaller than diameters of each one of the sideband signal vias in the set of sideband signal vias.

13. The computing device of claim 12 , wherein the set of sideband signal vias comprises one or more of a conductor for a clock request (CLKREQ) signal, a conductor for a reference clock (REFCLK) signal, or a conductor for a present (PRSNT) signal.

14. The computing device of claim 12 , wherein the plurality of sentry ground vias comprises at least three sentry ground vias adjacent to a particular one of the sideband signal conductors in the set of sideband signal conductors.

15. The computing device of claim 12 , wherein the one or more sideband signal conductors comprises a conductor for a power break (PWRBRK) signal.

16. A system comprising:
a system board comprising:
a pinfield, wherein the pinfield comprises:
a set of one or more conductors to correspond to and carry signals for a set of differential signaling pairs,
a set of ground vias;
a set of reference clock signal vias, and
two or more sentry ground vias adjacent to each one the reference clock signal vias in the set of reference clock signal vias, wherein the sentry vias are to improve signal integrity;

a connector coupled to the pinfield, wherein the connector comprises pins to be inserted into the set of ground vias and the set of reference clock signal vias; and
an add-in card coupled to the system board via the connector;
wherein the two or more sentry ground vias each have a diameter smaller than diameters of the pins of the connector.

17. The system of claim 16 , wherein the add-in card is coupled to the system board by the connector.

18. The system of claim 16 , wherein the connector comprises one of a thru-hole connector or a press-fit connector.

19. The system of claim 16 , wherein the add-in card comprises an endpoint compliant with an interconnect protocol.

20. The system of claim 19 , wherein the interconnect protocol comprises a Peripheral Component Interconnect Express (PCIe)-based protocol.

21. The system of claim 16 , wherein the add-in card comprises a device to receive clock signals, reset signals, and present signals via the connector coupled to the pinfield.

22. The system of claim 21 , wherein the device comprises one of an input-output (I/O) device, an audio processor, a network processor, a data storage device, or a network interface controller (NIC).

23. The system of claim 16 , wherein the system comprises a server system.

24. The system of claim 16 , wherein the one or more respective sentry vias adjacent to each one the reference clock signal vias in the set of reference clock signal vias comprise a different diameter than the one or more respective sentry vias adjacent to each one of the clock request signal vias in the set of reset signal vias.

25. The system of claim 24 , wherein one or more respective sentry vias adjacent to each one of the clock request signal vias in the set of reset signal vias comprises a different diameter than the one or more respective sentry vias adjacent to each one of the present signal vias in the set of present signal vias.

26. The system of claim 16 , further comprising:
a set of clock request signal vias;
a set of present signal vias; and
two or more respective sentry vias adjacent to each one of the clock request signal vias in the set of clock request signal vias, and two or more respective sentry vias adjacent to each one of the present signal vias in the set of present signal vias;
wherein the two or more sentry ground vias have a diameter smaller than diameters of the clock request signal vias and the present signal vias.

Assignees

• Intel Corp

Inventors

• Wig Timothy

Classifications

• H01R12/718

  Contact members provided on the PCB without an insulating housing (contacts for abutting H01R12/714) · CPC title

• H01R13/6471 Primary

  by special arrangement of ground and signal conductors, e.g. GSGS [Ground-Signal-Ground-Signal] · CPC title