Semiconductor device and method for manufacturing semiconductor device

Patent metadata

Field	Value
Publication number	US-11569373-B2
Application number	US-202117337662-A
Country	US
Kind code	B2
Filing date	Jun 3, 2021
Priority date	Jun 18, 2020
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

A semiconductor device includes first and second trenches, and a first layer provided therebetween, in a principal surface of a semiconductor substrate, a second layer in contact with and sandwiching the first trench with the first layer, a third layer provided under the second layer and in contact with the second layer and the first trench, a fourth layer provided under and in contact with the third layer but separated from the first trench, and a fifth layer provided in the principal surface and sandwiching the second trench with the first layer. The second and fourth layers are semiconductors of a first conductivity type, and the first, third, and fifth layers are semiconductors of a second conductivity type. A gate trench electrode is provided inside the first trench via the insulating film, and an emitter trench electrode is provided inside the second trench via the insulating film.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor substrate of a first conductivity type, having a first principal surface, and a second principal surface on an opposite side from the first principal surface;
a first trench provided in the first principal surface;
a second trench provided in the first principal surface;
a third trench provided in the first principal surface;
a fourth trench provided in the first principal surface;
a first semiconductor layer of a second conductivity type, provided in the first principal surface between the first trench and the second trench;
a second semiconductor layer of the first conductivity type, provided in the first principal surface at a position sandwiching the first trench between the second semiconductor layer and the first semiconductor layer, and making contact with the first trench;
a third semiconductor layer of the second conductivity type, provided under the second semiconductor layer, and making contact with the second semiconductor layer and the first trench;
a fourth semiconductor layer of the first conductivity type, provided under the third semiconductor layer, and making contact with the third semiconductor layer but separated from the first trench;
a fifth semiconductor layer of the second conductivity type, provided in the first principal surface at a position sandwiching the second trench between the fifth semiconductor layer and the first semiconductor layer;
a sixth semiconductor layer of the first conductivity type provided on the third semiconductor layer, making contact with the third semiconductor layer and the third trench, separated from the second semiconductor layer, and connected to the emitter electrode;
a first insulating film provided on an inner wall of the first trench;
a first gate trench electrode provided inside the first trench via the first insulating film, and opposing the third semiconductor layer;
a second insulating film provided on an inner wall of the second trench;
a first emitter trench electrode provided inside the second trench via the second insulating film;
a third insulating film provided on an inner wall of the third trench;
a second gate trench electrode provided inside the third trench via the third insulating film, opposing the third semiconductor layer, and connected to the gate electrode;
a fourth insulating film provided on an inner wall of the fourth trench;
a second emitter trench electrode provided inside the fourth trench via the fourth insulating film, and connected to the emitter electrode;
a gate electrode connected to the first gate trench electrode;
an emitter electrode connected to the first emitter trench electrode, the second semiconductor layer, the third semiconductor layer, and the fifth semiconductor layer; and
a collector electrode provided in the second principal surface, wherein
the first semiconductor layer is in an electrically floating state,
the first trench is arranged between the second trench and the third trench,
the second trench is arranged between the first trench and the fourth trench,
the third semiconductor layer makes contact with the third trench,
the fourth semiconductor layer is separated from the third trench,
the fifth semiconductor layer makes contact with the fourth trench, and
the third trench, the first trench, the second trench, and the fourth trench are equally spaced and formed in a stripe shape along a predetermined direction.

2. The semiconductor device as claimed in claim 1 , further comprising:
a seventh semiconductor layer of the first conductivity type, provided under the fifth semiconductor layer, and making contact with the fifth semiconductor layer.

3. The semiconductor device as claimed in claim 2 , wherein the seventh semiconductor layer is separated from the second trench.

4. The semiconductor device as claimed in claim 1 , wherein a depth of the first semiconductor layer is greater than or equal to a depth of the first trench.

5. The semiconductor device as claimed in claim 1 , wherein a depth of the fifth semiconductor layer is equal to a depth of the third semiconductor layer.

6. The semiconductor device as claimed in claim 1 , wherein a depth of the fifth semiconductor layer is greater than a depth of the third semiconductor layer, and is less than or equal to a depth of the first semiconductor layer.

7. The semiconductor device as claimed in claim 1 , further comprising:
a fifth trench provided in the first principal surface at a position between the first trench and the second trench;
a fifth insulating film provided on an inner wall of the fifth trench;
a third emitter trench electrode provided inside the fifth trench via the fifth insulating film, and connected to the emitter electrode, wherein
the first semiconductor layer is provided between the first trench and the fifth trench that are adjacent to each other, and between the second trench and the fifth trench that are adjacent to each other, and
the first trench, the fifth trench, and the second trench are equally spaced and formed in a stripe shape along the predetermined direction.

8. The semiconductor device as claimed in claim 7 , wherein
a plurality of fifth trenches are provided in the first principal surface between the first trench and the second trench,
the fifth insulating film and the third emitter trench electrode are provided for each of the plurality of fifth trenches,
the first semiconductor layer is provided between two fifth trenches that are adjacent to each other, and
the first trench, the plurality of fifth trenches, and the second trench are equally spaced and formed in a stripe shape along the predetermined direction.

9. The semiconductor device as claimed in claim 8 , further comprising:
a sixth trench provided in the first principal surface between two fifth trenches that are adjacent to each other;
a sixth insulating film provided on an inner wall of the sixth trench; and
a third gate trench electrode provided inside the sixth trench via the sixth insulating film, and connected to the gate electrode, wherein
the first semiconductor layer is provided between the fifth trench and the sixth trench that are adjacent to each other, and
the plurality of fifth trenches, and the sixth trench are equally spaced and formed in a stripe shape along the predetermined direction.

10. A method for manufacturing a semiconductor device, comprising:
forming a first trench, a second trench, a third trench, and a fourth trench in a first principal surface of a semiconductor substrate of a first conductivity type having the first principal surface and a second principal surface on an opposite side from the first principal surface;
forming a first semiconductor layer of a second conductivity type in the first principal surface between the first trench and the second trench;
forming a second semiconductor layer of the first conductivity type in the first principal surface, making contact with the first trench, at a position sandwiching the first trench between the second semiconductor layer and the first semiconductor layer;
forming a third semiconductor layer of the second conductivity type under the second semiconductor layer, making contact with the second semiconductor layer and the first trench;
forming a fourth semiconductor layer of the first conductivity type under the third semiconductor layer, making contact with the third semiconductor layer but separated from the first trench;
forming a fifth semiconductor layer of the second conductivity type in the first principal surface at a position sandwiching the second trench between the fifth semiconductor layer and the first semiconductor layer;
for

Assignees

• Yatago Masatoshi
• Shiraishi Naohiro
• Kondo Katsunori
• Watanabe Noriyoshi
• Mitsumi Electric Co Ltd

Inventors

• Yatago Masatoshi
• Shiraishi Naohiro
• Kondo Katsunori
• Watanabe Noriyoshi

Classifications

• H01L29/6634

  Electricity · mapped topic

• H01L29/66348

  Electricity · mapped topic

• H01L29/407

  Electricity · mapped topic

• H01L29/7397 Primary

  Electricity · mapped topic

• H01L29/1095

  Electricity · mapped topic