Method for forming integrated circuit

Patent metadata

Field	Value
Publication number	US-11569267-B2
Application number	US-202117368725-A
Country	US
Kind code	B2
Filing date	Jul 6, 2021
Priority date	Dec 31, 2019
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

A method for forming an integrated circuit includes following operations. A substrate having a first region, a second region and an isolation structure is received. A portion of the substrate is removed such that the second region is recessed. A portion of the isolation structure is removed to obtain a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface. A first device is formed in the first region, a second device is formed in the second region, and a dummy structure is formed over the first top surface, the second top surface and the boundary. A dielectric structure is formed over the substrate. A top surface of the first device, a top surface of the second device and a top surface of the dummy structure are aligned with each other.

First claim

What is claimed is:

1. A method for forming an integrated circuit, comprising:
receiving a substrate having a first region, a second region and an isolation structure separating the first region from the second region;
removing a portion of the substrate and a portion of the isolation structure such that the second region is recessed and the isolation structure obtains a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface;
forming a first device in the first region, a second device in the second region and a dummy structure on a portion of the first top surface, a portion of the second top surface, and the boundary between the first top surface and the second top surface;
forming a dielectric structure over the substrate to cover the first device, the second device and the dummy structure; and
removing a portion of the dielectric structure, a portion of the first device, a portion of the second device and a portion of the dummy structure such that a top surface of the first device, a top surface of the second device, and a top surface of the dummy structure are aligned with each other.

2. The method of claim 1 , wherein the substrate comprises a semiconductor bulk, a semiconductor layer and a dielectric layer disposed between the semiconductor bulk and the semiconductor layer, and the removing of the portion of the substrate removes a portion of the semiconductor layer and a portion of the dielectric layer in the second region such that the semiconductor bulk in the second region is exposed.

3. The method of claim 1 , wherein the forming of the first device, the second device and the dummy structure further comprises:
forming a high-k gate dielectric layer over the substrate;
forming a semiconductor layer on the high-k gate dielectric layer; and
patterning the high-k gate dielectric layer and the semiconductor layer to form a first sacrificial gate in the first region, a second sacrificial gate in the second region, and the dummy structure on the isolation structure,

wherein the dummy structure covers the portion of the first top surface, the portion of the second top surface, and the boundary between the first top surface and the second top surface, and thicknesses of the first sacrificial gate, the second sacrificial gate and the dummy structure are similar.

4. The method of claim 3 , further comprising:
removing the first sacrificial gate and the second sacrificial gate to form a first gate trench and a second gate trench; and
forming a first metal gate in the first gate trench and a second metal gate in the second gate trench,

wherein a thickness of the second metal gate is greater than a thickness of the first metal gate.

5. The method of claim 4 , further comprising forming a dielectric layer over the dummy structure prior to the removing of the first sacrificial gate and the second sacrificial gate.

6. The method of claim 4 , wherein the dummy structure comprises a first portion and a second portion coupled to each other, a thickness of the first portion is similar to the thickness of the first metal gate, and a thickness of the second portion is similar to the thickness of the second metal gate.

7. A method for forming an integrated circuit, comprising:
receiving a substrate comprising a semiconductor bulk, a semiconductor layer and a dielectric layer disposed between the semiconductor bulk and the semiconductor layer, wherein the substrate has a first region, a second region and an isolation structure separating the first region from the second region;
removing a portion of the semiconductor layer and a portion of the dielectric layer from the second region to expose the semiconductor bulk in the second region;
removing a portion of the isolation structure such that the isolation structure obtains a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface;
forming a first device in the first region, a second device in the second region and a dummy structure on a portion of the first top surface, a portion of the second top surface, and the boundary between the first top surface and the second top surface;
forming a dielectric structure over the substrate to cover the first device, the second device and the dummy structure; and
removing a portion of the dielectric structure, a portion of the first device, a portion of the second device and a portion of the dummy structure such that a top surface of the first device, a top surface of the second device, and a top surface of the dummy structure are aligned with each other.

8. The method of claim 7 , wherein the removing of the portion of the semiconductor layer and the portion of the dielectric layer, and the removing of the portion of the isolation structure are simultaneously performed.

9. The method of claim 7 , further comprising forming a patterned mask covering a portion of the substrate in the first region and covering a portion of the isolation structure.

10. The method of claim 7 , wherein the removing of the portion of the semiconductor layer and the portion of the dielectric layer from the second region further comprises removing a portion of the semiconductor bulk from the second region.

11. The method of claim 7 , wherein the first device comprises a first sacrificial gate, and the second device comprises a second sacrificial gate.

12. The method of claim 11 , wherein thicknesses of the first sacrificial gate, the second sacrificial gate and the dummy structure are similar.

13. The method of claim 11 , further comprising:
removing the first sacrificial gate and the second sacrificial gate to form a first gate trench and a second gate trench; and
forming a first metal gate in the first gate trench and a second metal gate in the second gate trench,

wherein a thickness of the second metal gate is greater than a thickness of the first metal gate.

14. The method of claim 13 , further comprising forming a dielectric layer over the dummy structure prior to the removing of the first sacrificial gate and the second sacrificial gate.

15. The method of claim 13 , wherein the dummy structure comprises a first portion and a second portion coupled to each other, a thickness of the first portion is similar to the thickness of the first metal gate, and a thickness of the second portion is similar to the thickness of the second metal gate.

16. A method for forming an integrated circuit, comprising:
receiving a substrate having a first region, a second region and an isolation structure separating the first region from the second region;
recessing a portion of the substrate and a portion of the isolation structure, wherein the isolation structure obtains a first top surface, a second top surface lower than the first top surface, and a boundary between the first top surface and the second top surface;
forming a well region in the substrate in the second region;
forming a first device in the first region, a second device in the second region and a dummy structure on a portion of the first top surface, a portion of the second top surface, and the boundary between the first top surface and the second top surface;
forming a dielectric structure over the substrate to cover the first device, the second device and the dummy structure; and
removing a portion of the dielectric structure, a portion of the first device, a portion of the second device and a portion of the dummy structure such that a top surface of the first device, a top

Assignees

• Taiwan Semiconductor Mfg Co Ltd
• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Lin Meng-Han
• Chen Te-An

Classifications

• H01L27/1203 Primary

  Electricity · mapped topic

• H01L29/0649

  Electricity · mapped topic

• H01L21/84

  Electricity · mapped topic

• H01L29/66545

  Electricity · mapped topic

• H01L21/76283

  Electricity · mapped topic