Dynamically updating logical identifiers of cores of a processor

Patent metadata

Field	Value
Publication number	US-11567896-B2
Application number	US-202016916197-A
Country	US
Kind code	B2
Filing date	Jun 30, 2020
Priority date	Feb 27, 2015
Publication date	Jan 31, 2023
Grant date	Jan 31, 2023

Abstract

In one embodiment, a processor includes a plurality of cores each including a first storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core; a plurality of thermal sensors to measure a temperature at a corresponding location of the processor; and a power controller including a dynamic core identifier logic to dynamically remap a first logical identifier associated with a first core to associate the first logical identifier with a second core, based at least in part on a temperature associated with the first core, the dynamic remapping to cause a first thread to be migrated from the first core to the second core transparently to an operating system. Other embodiments are described and claimed.

First claim

What is claimed is:

1. A processor comprising:
a plurality of cores, each of the plurality of cores including a first non-volatile storage to store a physical identifier for the core and a second volatile storage to store a logical identifier associated with the core;
a plurality of thermal sensors to measure a temperature at a corresponding location of the processor;
a plurality of power sensors to measure a power at a corresponding location of the processor;
a controller to dynamically remap a first logical identifier from association with a first core to association with a second core, based at least in part on at least one of a temperature and a power associated with the first core, the dynamic remapping to cause a first thread in execution on the first core to be migrated from the first core to the second core transparently to an operating system;
a mapping table including a plurality of entries each to store a logical identifier-to-physical identifier association, wherein an entry of the mapping table associated with the second core is to store the first logical identifier in response to the dynamic remapping of the first logical identifier; and
an input/output (I/O) interface coupled to the plurality of cores, wherein the I/O interface is associated with a second mapping table including a plurality of entries each to store a logical identifier-to-physical identifier association, wherein the controller is to communicate an update to the entry of the mapping table to the I/O interface to enable the second mapping table to be updated.

2. The processor of claim 1 , further comprising a plurality of wear sensors to measure wear information regarding the plurality of cores.

3. The processor of claim 1 , further comprising a third storage to store usage history information regarding usage of the plurality of cores.

4. The processor of claim 3 , further comprising a fourth storage to store characterization information for the plurality of cores.

5. The processor of claim 3 , wherein the controller is to dynamically remap the first logical identifier based at least in part on the usage history information of the first core.

6. The processor of claim 1 , wherein the controller is to dynamically remap the first logical identifier further based on a power consumption level of the first core.

7. The processor of claim 1 , wherein the first core and the second core comprise heterogenous cores.

8. The processor of claim 1 , wherein a third core of the plurality of cores comprises a spare core.

9. A processor comprising:
a plurality of cores; and
a power controller coupled to the plurality of cores, wherein the power controller is to:
receive environmental information regarding operation of the processor and usage information for the plurality of cores;
select a first core to be dynamically remapped from association with a first logical identifier to association with a second logical identifier based on at least some of the environmental information and the usage information, when a second core of the plurality of cores is to operate at a higher turbo mode frequency than the first core, wherein one or more threads comprise high priority threads;
cause the first core to enter into a low power state and associate the second logical identifier with the first core, to cause the dynamic remapping, wherein in response to an interrupt the first core is to prevent the power controller from the dynamic remapping of the first core; and
cause the second core to exit a low power state and provide the first logical identifier to the second core for storage in a logical identifier storage of the second core.

10. The processor of claim 9 , wherein after the first logical identifier is stored in the logical identifier storage of the second core, the second core is to access context information from a shared cache memory, and resume execution of the one or more threads on the second core.

11. The processor of claim 9 , wherein the power controller is to select the first core when a temperature of the first core exceeds a thermal threshold, and a temperature of the second core is less than the thermal threshold.

12. The processor of claim 9 , further comprising a plurality of wear sensors to measure wear information regarding the plurality of cores.

13. The processor of claim 12 , wherein the power controller is to select the first core based at least in part on the wear information, to enable wear leveling of the plurality of cores.

14. A system comprising:
a processor having:
a plurality of cores, each of the plurality of cores including a first non-volatile storage to store a physical identifier for the core and a second storage to store a logical identifier associated with the core;
a shared cache memory coupled to the plurality of cores;
a power controller, based on one or more of temperature information and usage information associated with a first core, to dynamically remap a first logical identifier from association with the first core to association with a second core, to cause a first thread to be migrated from the first core to the second core transparently to an operating system;
a first mapping table including a plurality of entries each to store a logical identifier-to-physical identifier association for a core;
a memory interface to interface the processor to a memory;
an input/output (I/O) interface to couple to one or more devices and to provide an incoming message to a selected core; and
a second mapping table coupled to the I/O interface including a second plurality of entries each to store a logical identifier-to-physical identifier association for a core, wherein the power controller is to dynamically update a first entry of the first mapping table and cause a dynamic update to a corresponding entry of the second mapping table to associate the first logical identifier with the second core; and

a system memory coupled to the processor.

15. The system of claim 14 , wherein the processor further comprises another storage to store a plurality of entries each associated with a core and including a plurality of characterization values for the core, wherein at least some of the plurality of cores have a different characterization value for a first operating parameter, based on manufacturing variation.

16. The system of claim 14 , wherein the second core is to access context information of the first thread from the shared cache memory and resume execution of the first thread, based at least in part on the first logical identifier.

17. The processor of claim 9 , further comprising an input/output (I/O) interface, wherein the I/O interface is associated with a mapping table including a plurality of entries each to store a logical identifier-to-physical identifier association, wherein the power controller is to inform the I/O interface of the dynamic remapping, to cause the mapping table to be updated.

Assignees

• Intel Corp

Inventors

• Varma Ankush
• Sistla Krishnakanth V
• Sotomayor Guy G
• Henroid Andrew D
• Gough Robert E
• Schiff Tod F

Classifications

• G06F9/45558

  Hypervisor-specific management and integration aspects · CPC title

• G06F1/26

  Power supply means, e.g. regulation thereof (for memories G11C) · CPC title

• G06F1/3243

  Power saving in microcontroller unit · CPC title

• G06F9/5094

  where the allocation takes into account power or heat criteria (power management in computers in general G06F1/3203; thermal management in computers in general G06F1/206) · CPC title

• G06F9/5077

  Logical partitioning of resources; Management or configuration of virtualized resources (specific details on emulation or internal functioning of virtual machines G06F9/455) · CPC title