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US-2024394271-A1 · Nov 28, 2024 · US
Ordering Memory Commands in a Computer System
US2016371014A1 · US · A1
| Field | Value |
|---|---|
| Publication number | US-2016371014-A1 |
| Application number | US-201514743091-A |
| Country | US |
| Kind code | A1 |
| Filing date | Jun 18, 2015 |
| Priority date | Jun 18, 2015 |
| Publication date | Dec 22, 2016 |
| Grant date | — |
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- Abstract
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Abstract
Official abstract text for this publication.
The disclosed embodiments provide a system for processing a memory command on a computer system. During operation, a command scheduler executing on a memory controller of the computer system obtains a predicted latency of the memory command based on a memory address to be accessed by the memory command. Next, the command scheduler orders the memory command with other memory commands in a command queue for subsequent processing by a memory resource on the computer system based on the predicted latency of the memory command.
First claim
Opening claim text (preview).
What is claimed is: 1 . A method for processing a memory command on a computer system, comprising: obtaining, by a command scheduler executing on a memory controller of the computer system, a predicted latency of the memory command based on a memory address to be accessed by the memory command; and ordering, by the command scheduler, the memory command with other memory commands in a command queue for subsequent processing by a memory resource on the computer system based on t…
Assignees
Inventors
Classifications
- G06F3/0611Primary
Physics · mapped topic
Physics · mapped topic
- G06F3/0679Primary
Physics · mapped topic
Physics · mapped topic
Physics · mapped topic
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Frequently asked questions
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- What does patent US2016371014A1 cover?
- The disclosed embodiments provide a system for processing a memory command on a computer system. During operation, a command scheduler executing on a memory controller of the computer system obtains a predicted latency of the memory command based on a memory address to be accessed by the memory command. Next, the command scheduler orders the memory command with other memory commands in a comman…
- Who is the assignee on this patent?
- Advanced Micro Devices Inc
- What technology area does this patent fall under?
- Primary CPC classification G06F3/0611. Mapped technology areas include Physics.
- When was this patent published?
- Publication date Thu Dec 22 2016 00:00:00 GMT+0000 (Coordinated Universal Time) (A1). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).