Calibration of a time-to-digital converter using a virtual phase-locked loop

Patent metadata

Field	Value
Publication number	US-11563441-B2
Application number	US-202217699350-A
Country	US
Kind code	B2
Filing date	Mar 21, 2022
Priority date	Mar 30, 2021
Publication date	Jan 24, 2023
Grant date	Jan 24, 2023

Abstract

A clock product includes a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal. The time-to-digital converter includes a coarse time-to-digital converter and a fine time-to digital converter. The clock product includes a calibration circuit including a phase-locked loop. The calibration circuit is configured to generate the time-to-digital converter calibration signal. The clock product includes a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter and to average the error signal over multiple clock cycles to generate an average error signal.

First claim

What is claimed is:

1. A clock product comprising:
a time-to-digital converter responsive to an input clock signal, a reference clock signal, and a time-to-digital converter calibration signal, the time-to-digital converter including a coarse time-to-digital converter and a fine time-to digital converter;
a calibration circuit including a phase-locked loop, the calibration circuit being configured to generate the time-to-digital converter calibration signal; and
a controller configured to execute instructions that cause the phase-locked loop to generate an error signal for each possible value of a fine time code of a digital time code generated by the time-to-digital converter, and to average the error signal over multiple clock cycles to generate an average error signal.

2. The clock product as recited in claim 1 wherein the controller is further configured to execute additional instructions to cause the controller to determine a maximum average error signal based on the average error signal generated for each value of the fine time code.

3. The clock product as recited in claim 2 wherein the controller is further configured to provide the maximum average error signal as an estimate of integral nonlinearity of the time-to-digital converter.

4. The clock product as recited in claim 1 wherein execution of the instructions causes the controller to generate a coarse time code and a residue signal based on the input clock signal and the reference clock signal, generate the fine time code based on the residue signal, and apply the time-to-digital converter calibration signal as a digital gain adjustment to the fine time code to generate an adjusted fine time code.

5. The clock product as recited in claim 4 wherein the execution of the instructions further causes the controller to combine the coarse time code and the adjusted fine time code to generate the digital time code.

6. The clock product as recited in claim 4 further comprising:
at least one additional time-to-digital converter;
a storage element configured to store state variables for the time-to-digital converter and the at least one additional time-to-digital converter; and
a select circuit configured to provide a selected digital time code, a selected fine time code, and associated state variables generated by the time-to-digital converter or the at least one additional time-to-digital converter to the calibration circuit according to a select signal generated by the controller.

7. The clock product as recited in claim 6 wherein the controller is further configured to execute additional instructions to cause the controller to sequentially update the select signal and cause the calibration circuit to serially process data for the time-to-digital converter and the at least one additional time-to-digital converter.

8. The clock product as recited in claim 1 wherein the calibration circuit further includes an adaptive loop configured to generate the time-to-digital converter calibration signal based on the error signal and the fine time code of the digital time code.

9. A method for converting an analog signal to a digital signal, the method comprising:
generating a digital code corresponding to an input analog signal using an analog-to-digital converter responsive to a reference signal and an analog-to-digital converter calibration signal;
generating a digital error signal based on the digital code and an estimated digital code; and
generating the analog-to-digital converter calibration signal based on the digital error signal and the digital code.

10. The method as recited in claim 9 wherein the analog-to-digital converter comprises a coarse analog-to-digital converter and a fine analog-to-digital converter, and generating the digital code comprises:
generating a coarse code and a residue signal based on the input analog signal and the reference signal;
generating a fine code based on the residue signal;
applying the analog-to-digital converter calibration signal as a digital gain adjustment to the fine code to generate an adjusted fine code; and
combining the coarse code and the adjusted fine code to generate the digital code.

11. The method as recited in claim 9 wherein generating the digital error signal comprises:
computing a difference between the digital code and the estimated digital code to generate the digital error signal;
generating an integrated error signal based on the digital error signal;
generating a proportional error signal based on the digital error signal;
computing a sum of the integrated error signal and the proportional error signal;
integrating the sum to generate an integrated sum;
generating an expected digital code; and
generating the estimated digital code based on the sum of the expected digital code and the integrated sum.

12. The method as recited in claim 9 wherein generating the digital error signal comprises compensating for rollover error caused by using less than all bits of the digital code to generate the digital error signal.

13. The method as recited in claim 9 wherein the digital error signal has zero mean.

14. The method as recited in claim 9 wherein the estimated digital code is generated with the same period as the digital code.

15. The method as recited in claim 9 further comprising generating an output clock signal based on the digital code and a feedback digital code.

16. A clock generator comprising:
an analog-to-digital converter configured to generate a digital code based on an input signal, a reference signal, and an analog-to-digital converter calibration signal; and
a calibration circuit configured to generate the analog-to-digital converter calibration signal based on the digital code, the calibration circuit including a phase-locked loop configured to generate a digital phase error signal based on the digital code, an estimated digital code, and the input signal, and including an adaptive loop configured to generate the analog-to-digital converter calibration signal based on the digital phase error signal and a fine code of the digital code.

17. The clock generator as recited in claim 16 wherein the analog-to-digital converter comprises:
a coarse analog-to-digital converter configured to generate a coarse code and a residue signal based on the input signal and the reference signal;
a fine analog-to-digital converter configured to generate the fine code based on the residue signal and to apply the analog-to-digital converter calibration signal as a digital gain adjustment to the fine code to generate an adjusted fine code; and
a combiner configured to combine the coarse code and the adjusted fine code to generate the digital code.

18. The clock generator as recited in claim 16 wherein the phase-locked loop includes two integrators and is configured to cause the digital phase error signal to have zero mean.

19. The clock generator as recited in claim 16 wherein the estimated digital code is a spur-attenuated version of the digital code.

20. The clock generator as recited in claim 16 wherein the phase-locked loop further comprises a wrap detection and correction circuit configured to compensate for rollover error caused by using less than all bits of the digital code by the phase-locked loop and the adaptive loop.

Assignees

• Skyworks Solutions Inc

Inventors

• Monk Timothy Adam
• Pastorello Douglas F
• Balakrishnan Krishnan
• Kolar Ranganathan Raghunandan

Classifications

• H03L7/085

  concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal (H03L7/10 takes precedence; circuits for comparing the phase or frequency of two mutually-independent oscillations H03D13/00) · CPC title

• H03M1/1014 Primary

  at one point of the transfer characteristic, i.e. by adjusting a single reference value, e.g. bias or gain error (gain setting for range control H03M1/18) · CPC title

• G04F10/005

  Time-to-digital converters [TDC] (analog-to-digital converters with intermediate conversion to time or phase H03M1/50, H03M1/60) · CPC title

• H03L7/23

  with pulse counters or frequency dividers · CPC title

• H03L7/0992

  comprising a counter or a frequency divider · CPC title