Low-power high-performance clock path architecture
US-2024393824-A1 · Nov 28, 2024 · US
Higher-order phase noise modulator to reduce spurs and quantization noise
US8994420B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-8994420-B2 |
| Application number | US-201213469936-A |
| Country | US |
| Kind code | B2 |
| Filing date | May 11, 2012 |
| Priority date | May 11, 2012 |
| Publication date | Mar 31, 2015 |
| Grant date | Mar 31, 2015 |
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Abstract
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A frequency synthesizer capable of generating a clock signal having reduced digital spurs and reduced jitter is described. An apparatus includes a frequency modulator configured to generate a divide control signal and a digital quantization error signal in response to a divide ratio. The apparatus includes a phase modulator configured to generate a phase error signal based on the digital quantization error signal. The phase modulator is an n-order sigma-delta modulator module, n being an integer greater than one. The apparatus may include an interpolative divider configured to generate a feedback signal in a phase-locked loop (PLL) based on an output signal of the PLL, the divide control signal, and the phase error signal. The interpolative divider may include the frequency modulator and the phase modulator. The phase modulator may have a unity gain signal transfer function.
First claim
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What is claimed is: 1. An apparatus comprising: a fractional-N divider in a feedback path of a phase-locked loop (PLL) responsive to an output of the PLL and a divide control signal to generate a frequency-divided version of the output of the PLL; a phase interpolator in the feedback path of the PLL responsive to the frequency-divided version of the output of the PLL and a phase interpolation control signal to generate a phase-adjusted version of a feedback signal of the PLL;…
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- H03L7/08Primary
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
Electricity · mapped topic
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Frequently asked questions
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- What does patent US8994420B2 cover?
- A frequency synthesizer capable of generating a clock signal having reduced digital spurs and reduced jitter is described. An apparatus includes a frequency modulator configured to generate a divide control signal and a digital quantization error signal in response to a divide ratio. The apparatus includes a phase modulator configured to generate a phase error signal based on the digital quanti…
- Who is the assignee on this patent?
- Eldredge Adam B, Gong Xue-Mei, Silicon Lab Inc
- What technology area does this patent fall under?
- Primary CPC classification H03L7/08. Mapped technology areas include Electricity.
- When was this patent published?
- Publication date Tue Mar 31 2015 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
- What related patents are in patentsdb?
- We list 8 related publications on this page (citations in our corpus or others sharing the same primary CPC).