Memory device storing parity and memory system including the same

Patent metadata

Field	Value
Publication number	US-11562803-B2
Application number	US-202117244195-A
Country	US
Kind code	B2
Filing date	Apr 29, 2021
Priority date	Oct 23, 2020
Publication date	Jan 24, 2023
Grant date	Jan 24, 2023

Abstract

A memory device includes a cell array including a plurality of pages and a control logic configured to control program and read operations of the cell array. The control logic controls the program and read operations to store first through N-th codewords in a first page among the pages and program a page parity corresponding in common to the first through N-th codewords to the first page in response to a program command for a page unit and to selectively read the first codeword among the first through N-th codewords in response to a read command for a sub-page unit, where N is an integer of at least 2. The first codeword includes first sub-page data and a first sub-parity corresponding thereto, and the first sub-parity includes information for correcting an error in the first sub-page data through error correction code (ECC) decoding independently performed on each codeword.

First claim

What is claimed is:

1. A memory device comprising:
a cell array including a plurality of pages; and
a control logic circuitry configured to control program operations of the cell array and read operations of the cell array,
wherein the control logic circuitry is configured to control the program operations and read operations such that
(A) in response to a program command for a page, the memory device stores first through N-th codewords in a first page among the plurality of pages and the memory device programs a page parity corresponding in common to the first through N-th codewords to the first page, and
(B) in response to a read command for a sub-page, the memory device selectively reads the first codeword among the first through N-th codewords, where N is an integer of at least 2, wherein a size of the sub-page is less than a size of the page.
wherein the first codeword includes first sub-page data and a first sub-parity corresponding to the first sub-page data, and the first sub-parity includes information associated with correcting an error in the first sub-page data through error correction code (ECC) decoding, the ECC decoding independently performable on each of the first through N-th codewords,
wherein the memory device is configured to program the first through N-th codewords to the first page in a single program operation in response to a plurality of write requests from a host; and
wherein the memory device is configured to provide the first codeword to the host in a single read operation in response to a single read request from the host.

2. The memory device of claim 1 , wherein the memory device is configured to read the first codeword and to output the first codeword to a memory controller circuitry and,
in response to the error in the first sub-page data not corrected, the memory device is configured to further read the second through N-th codewords and the page parity and to output the second through N-th codewords and the page parity to the memory controller circuitry.

3. The memory device of claim 1 , further comprising:
a page buffer configured to store the first through N-th codewords and the page parity of the first through N-th codewords, and to provide the first through N-th codewords and the page parity to the cell array in response to the program command from a memory controller circuitry, the program command associated with the page.

4. The memory device of claim 3 , wherein the page buffer is configured to store the first codeword, the first codeword being read in response to the read command associated with the sub-page; and
the memory device is configured to output the first codeword to the memory controller circuitry that is stored in the page buffer as the sub-page.

5. The memory device of claim 1 , wherein each memory cell of the cell array is configured to store M bits, where M is an integer of at least 2;
a plurality of memory cells connected to a word line correspond to the first page and second through M-th pages; and
the cell array is configured to store the first through N-th codewords and the page parity in one of the first through M-th pages.

6. The memory device of claim 1 , wherein each memory cell of the cell array is configured to store M bits, where M is an integer of at least 2;
a plurality of memory cells connected to a word line correspond to the first page and second through M-th pages;
the page parity further corresponds to (N+1)-th through K-th codewords, where K is an integer greater than N; and
the memory cell array is configured to store the (N+1)-th through K-th codewords in the second through M-th pages in a distributed fashion.

7. The memory device of claim 1 , wherein the page parity includes information based on low density parity-check code (LDPC), the LDPC information in relation to the first through N-th codewords.

8. The memory device of claim 1 , wherein the page parity includes information generated using first through N-th extra parities, the first through N-th extra parities calculated by a certain operation on each of the first through N-th codewords before the page parity is generated, and
the first through N-th extra parities are not stored in the cell array before or after the generation of the information in the page parity.

9. A memory system comprising:
a memory device including a cell array including a plurality of pages; and
a memory controller circuitry including a memory interface circuitry configured to communicate with the memory device, and an error correction code (ECC) circuitry configured to generate a codeword including a sub-parity by performing first ECC encoding on sub-page data and to generate a page parity by performing second ECC encoding on first through N-th codewords generated through the first ECC encoding, wherein in response to a write request from a host the memory controller circuitry is configured to transmit a program command associated with a page to the memory device and to program the first through N-th codewords and the page parity to a first page of the cell array, and in response to a read request from the host, the memory controller circuitry is configured to transmit a read command associated with a sub-page to the memory device and to selectively read the first codeword, where N is an integer of at least 2, wherein a size of the sub-page is less than a size of the page,
wherein the memory device is configured to program the first through N-th codewords to the first page in a single program operation in response to a plurality of write requests from the host; and
wherein the memory device is configured to provide the first codeword to the host in the single read operation in response to a single read request from the host.

10. The memory system of claim 9 , wherein the memory controller circuitry is configured to receive, from the host, the write request corresponding to a size that is less than or equal to the sub-page; and
the first through N-th codewords include a plurality of pieces of write data respectively corresponding to a plurality of write requests from the host.

11. The memory system of claim 9 , wherein the first codeword includes first sub-page data and a first sub-parity corresponding to the first sub-page data, and the error correction circuitry is configured to perform the error correction on the first sub-page data through ECC decoding independently performed on each codeword.

12. The memory system of claim 11 , wherein, in response to an error in the first sub-page data not being corrected, the memory controller circuitry is further configured to read the second through N-th codewords and the page parity and to correct the error in the first sub-page data using the second through N-th codewords and the page parity.

13. The memory system of claim 11 , wherein the memory controller circuitry is further configured to calculate first through N-th extra parities by performing a certain operation on each of the first through N-th codewords and to generate the page parity using the first through N-th extra parities; and
the first through N-th extra parities are not stored in the memory device.

14. The memory system of claim 13 , wherein, in response to an error occurring in the first sub-page data, the memory controller circuitry is further configured to read the second through N-th codewords, to calculate the second through N-th extra parities, to calculate the first extra parity based on the second through N-th extra parities and the page parity, and to correct the error in the first sub-page data using the first extra parity.

15. The memory system of claim 9 , wherein

Assignees

• Samsung Electronics Co Ltd

Inventors

• Hwang Youngjun
• Kwak Heeyoul
• Jun Bohwan
• Son Hongrak
• Shin Dongmin
• Yu Geunyeong

Classifications

• G11C16/102

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/78

  using programmable devices · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title