Progressive effort decoder architecture

Patent metadata

Field	Value
Publication number	US-10498367-B2
Application number	US-201715491705-A
Country	US
Kind code	B2
Filing date	Apr 19, 2017
Priority date	Sep 30, 2014
Publication date	Dec 3, 2019
Grant date	Dec 3, 2019

Abstract

A memory device may include memory components to store data. The memory device may also include a processor that may decode a codeword associated with the data. The processor may receive the codeword and determine whether the codeword is independently decodable using a BCH decoder. The processor may then decode the codeword using the BCH decoder when the codeword is determined to be independently decodable using the BCH decoder. Otherwise, the processor may decode the codeword using a second decoder and the BCH decoder when the codeword is not determined to be independently decodable using the BCH decoder.

First claim

What is claimed is:

1. A method, comprising:
receiving, via a processor, a codeword configured to indicate whether data associated with the codeword includes one or more errors;
determining whether the codeword is decodable using a first error correction code (ECC) algorithm;
decoding the codeword using the first ECC algorithm when the codeword is determined to be decodable by the first ECC algorithm; and
decoding a portion of the codeword using a second ECC algorithm and decoding a remaining portion of the codeword using the first ECC algorithm in response to the first ECC algorithm being unable to solely decode the codeword.

2. The method of claim 1 , wherein the codeword is decodable by the first ECC algorithm when the data is written into a memory during an initial-life of the memory.

3. The method of claim 1 , wherein the codeword is not decodable by the first ECC algorithm after the initial-life of the memory.

4. The method of claim 1 , wherein decoding the portion of the codeword using the second ECC algorithm and decoding the remaining portion of the codeword using the first ECC algorithm comprises:
decoding the portion of the codeword at least partially using the second ECC algorithm after an initial life of the memory, thereby generating a partially decoded codeword;
determining whether the partially decoded codeword is decodable using the first ECC algorithm;
decoding the remaining portion of the codeword using the first ECC algorithm when the partially decoded codeword is determined to be decodable by the first ECC algorithm.

5. The method of claim 1 , comprising storing soft data associated with the decoding of the codeword in a cache.

6. The method of claim 1 , wherein the codeword is received by directly accessing one or more memory cells of the memory via a hard read.

7. The method of claim 6 , wherein the hard read comprises multiple channels.

8. A memory device, comprising;
one or more memory components configured to store data;
a processor configured to decode a codeword associated with the data, wherein the processor is configured to:
receive the codeword;
decode the codeword using a BCH decoder during an initial life of the one or more memory components; and
decode a portion of the codeword using a second decoder and decode a remaining portion of the codeword using the BCH decoder after the initial life of the one or more memory components.

9. The memory device of claim 8 , wherein the one or more memory components comprise one or more NAND memory cells.

10. The memory device of claim 8 , wherein the one or more memory components are configured to employ at least one program/erase cycle when writing the data.

11. The memory device of claim 8 , wherein the second decoder corresponds to a low density parity check (LDPC) code.

12. The memory device of claim 8 , wherein the second decoder is configured to consume more energy as compared to the BCH decoder.

13. The memory device of claim 8 , wherein the second decoder is configured to perform more than one iteration.

14. The memory device of claim 8 , wherein the processor is configured to decode the codeword using the BCH decoder based on a determination of whether the codeword is decodable using the BCH decoder using a Berlekamp algorithm.

15. The memory device of claim 14 wherein the BCH decoder is configured to send a status update regarding whether the codeword is decodable using the BCH decoder to a cache.

16. The memory device of claim 15 , wherein the BCH decoder is configured to send the status update via a Progressive Side-band Information (PSI) component.

17. A tangible, non-transitory, machine-readable medium, comprising instructions configured to:
receive a codeword configured to indicate whether data associated with the codeword includes one or more errors, wherein the codeword is received from a memory;
decode the codeword using the BCH decoder during an initial number of write operations performed on the memory; and
decode a first portion of the codeword using a first low density parity check (LDPC) decoder and a first remaining portion of the codeword using the BCH decoder or decode a second portion of the codeword using a second LDPC decoder and a second remaining portion of the codeword using the BCH decoder after the initial number of write operations are performed on the memory.

18. The tangible, non-transitory, machine-readable medium of claim 17 , wherein the instructions are configured to decode the first remaining portion of the codeword using the BCH decoder and the first portion of the codeword using the first LDPC decoder after determining that the codeword is not decodable using the BCH decoder alone.

19. The tangible, non-transitory, machine-readable medium of claim 17 , wherein the instructions are configured to decode the second remaining portion of the codeword using the BCH decoder and the second portion of the codeword using the second LDPC decoder after determining that the codeword is not decodable using the BCH decoder and the first LDPC decoder.

20. The tangible, non-transitory, machine-readable medium of claim 19 , wherein the instructions are configured to decode the second remaining portion of the codeword using the BCH decoder and the second portion of the codeword using the second LDPC decoder and soft data regarding a reliability of each bit in the codeword when the second remaining portion of the codeword is not decodable by the BCH decoder and the second portion of the codeword is not decodable by the second LDPC decoder.

Assignees

• Micron Technology Inc

Inventors

• Parthasarathy Sivagnanam
• Richardson Nicholas Julian
• Khayat Patrick Robert
• Kaynak Mustafa Nazmi
• Ling Ka Leung
• Eisenhuth Robert B

Classifications

• H03M13/2927 Primary

  Decoding strategies · CPC title

• H03M13/2906

  using block codes (H03M13/2957 takes precedence) · CPC title

• H03M13/3715

  Adaptation to the number of estimated errors or to the channel state · CPC title

• H03M13/1111

  Soft-decision decoding, e.g. by means of message passing or belief propagation algorithms · CPC title

• H03M13/152 Primary

  Bose-Chaudhuri-Hocquenghem [BCH] codes · CPC title