Analog-to-digital conversion circuit with improved linearity

Patent metadata

Field	Value
Publication number	US-11558063-B2
Application number	US-202117521488-A
Country	US
Kind code	B2
Filing date	Nov 8, 2021
Priority date	Aug 11, 2020
Publication date	Jan 17, 2023
Grant date	Jan 17, 2023

Abstract

Herein disclosed is an example analog-to-digital converter (ADC) and methods that may be performed by the ADC. The ADC may derive a first code that approximates a combination of an analog input value of the ADC and a dither value for the ADC sampled on a capacitor array. The ADC may further derive a second code to represent a residue of the combination with respect to the first code applied to the capacitor array. The ADC may combine the numerical value of the first code and the numerical value of the second code to produce a combined code applied to the capacitor array for deriving a digital output code. Combining the numerical value of the first code and the numerical value of the second code in the digital domain can provide for greater analog-to-digital (A/D) conversion linearity.

First claim

What is claimed is:

1. A method for providing a digital output code to represent an analog input value, the method comprising:
acquiring and sampling, using a first segment of a capacitor array and a second segment of the capacitor array, a combined value having an analog input value and a dither value;
deriving, by a first successive-approximation-register analog-to-digital converter, a first code representing the sampled combined value;
deriving, by a second successive-approximation-register analog-to-digital converter, a second code representing a first residue of the sampled combined value with respect to the first code;
deriving, by the second successive-approximation-register analog-to-digital converter, a third code representing a second residue of the sampled combined value with respect to the first code combined with the second code; and
deriving a digital output code representing the analog input value by combining the first code, the second code, the third code, and a dither code representing the dither value.

2. The method of claim 1 , further comprising:
combining the first code and the second code to derive a combined code;
applying a first segment of the combined code to the first segment of the capacitor array; and
applying a second segment of the combined code to the second segment of the capacitor array.

3. The method of claim 1 , further comprising:
applying a first segment of the first code to the first segment of the capacitor array; and
applying a second segment of the first code to the second segment of the capacitor array.

4. The method of claim 3 , wherein a resolution of the first code is greater than to a resolution of the first segment of the first code.

5. The method of claim 1 , wherein deriving the digital output code comprises using mismatch information to calculate an estimate-weighted value of codes applied to the first segment of the capacitor array and the second segment of the capacitor array.

6. The method of claim 5 , wherein mismatch information comprises codes representing mismatch of capacitor ratios of capacitors of the capacitor array.

7. The method of claim 1 , wherein the second residue is substantially not correlated with the analog input value.

8. The method of claim 1 , wherein deriving the first code comprises truncating the dither code provided to the first successive-approximation-register analog-to-digital converter.

9. The method of claim 1 , wherein deriving the second code comprises configuring a third segment of the capacitor array to provide negative feedback for an amplifier to provide a first factor of gain.

10. The method of claim 9 , wherein deriving the third code comprises configuring the third segment of the capacitor array to provide negative feedback for the amplifier to provide a second factor of gain.

11. The method of claim 10 , wherein an absolute value of the first factor of gain is smaller than an absolute value of a second factor of gain.

12. An analog-to-digital converter (ADC), comprising:
a capacitor array comprising a first segment and a second segment; and
a first quantizer to derive a first code representing a sampled combined value, the sampled combined value representing a combination of an analog input value and a dither value acquired by the first segment and the second segment respectively;
a second quantizer to:
derive a second code representing a first residue of the sampled combined value with respect to the first code; and
derive a third code representing a second residue of the sampled combined value with respect to the first code combined with the second code; and

a control circuit to derive a digital output code representing the analog input value by combining the first code, the second code, the third code, and a dither code representing the dither value.

13. The ADC of claim 12 , wherein the first quantizer is a first successive-approximation-register analog-to-digital converter.

14. The ADC of claim 13 , wherein a total capacitance of the first successive-approximation-register analog-to-digital converter is less than 10 percent of a total capacitance of the capacitor array.

15. The ADC of claim 12 , wherein the second quantizer is a second successive-approximation-register analog-to-digital converter.

16. The ADC of claim 15 , wherein a total capacitance of the second successive-approximation-register analog-to-digital converter is less than 10 percent of a total capacitance of the capacitor array.

17. The ADC of claim 12 , wherein:
the control circuit is coupled to switches corresponding to the capacitor array; and
the control circuit is further to control the switches to:
cause a first segment of the first code to be applied to the first segment of the capacitor array; and
cause a second segment the first code to be applied to the second segment of the capacitor array.

18. The ADC of claim 12 , wherein
the control circuit is coupled to switches corresponding to the capacitor array; and
the control circuit is further to control the switches to:
cause a first segment of the second code to be applied to the first segment of the capacitor array; and
cause a second segment the second code to be applied to the second segment of the capacitor array.

19. The ADC of claim 12 , further comprising a scrambler to randomize errors induced by mismatch of the first segment of the capacitor array.

20. The ADC of claim 12 , further comprising:
an amplifier; and
wherein the capacitor array further includes a third segment coupled to the amplifier to provide negative feedback and implement a gain factor.

Assignees

• Analog Devices Inc

Inventors

• Steensgaard-Madsen Jesper

Classifications

• H03M1/1245

  Details of sampling arrangements or methods · CPC title

• H03M1/201 Primary

  by dithering · CPC title

• H03M1/162

  the steps being performed sequentially in a single stage, i.e. recirculation type (H03M1/161 takes precedence) · CPC title

• H03M1/1028 Primary

  at two points of the transfer characteristic, i.e. by adjusting two reference values, e.g. offset and gain error (gain setting for range control H03M1/18) · CPC title

• H03M1/0639 Primary

  using dither, e.g. using triangular or sawtooth waveforms (for increasing resolution H03M1/201) · CPC title