High impedance passive switched capacitor common mode feedback network

Patent metadata

Field	Value
Publication number	US-10122370-B2
Application number	US-201715447680-A
Country	US
Kind code	B2
Filing date	Mar 2, 2017
Priority date	Oct 27, 2016
Publication date	Nov 6, 2018
Grant date	Nov 6, 2018

Abstract

A switched capacitor circuit includes a first capacitor coupled in series with a second capacitor in a first mode of operation across differential output terminals of a circuit. The first capacitor and the second capacitor are coupled in an anti-parallel layout in a second mode of operation. The switched capacitor circuit also includes a third capacitor coupled on a first side to a common node of the first capacitor and the second capacitor. The third capacitor is further coupled on a second side to a current source control voltage in the first mode of operation, and coupled between a bias reference voltage and a common mode reference voltage in the second mode of operation.

First claim

What is claimed is:

1. A switched capacitor circuit, comprising:
a first capacitor coupled in series with a second capacitor in a first mode of operation across differential output terminals of a circuit, and coupled in an anti-parallel layout in a second mode of operation; and
a third capacitor coupled on a first side to a common node of the first capacitor and the second capacitor and on a second side to a current source control voltage in the first mode of operation, and coupled between a bias reference voltage and a common mode reference voltage in the second mode of operation.

2. The switched capacitor circuit of claim 1 , further comprising a fourth capacitor coupled in series with a fifth capacitor, the fourth capacitor coupled across a first of the differential output terminals of the circuit and the current source control voltage, the fifth capacitor coupled across a second of the differential output terminals of the circuit and the current source control voltage.

3. The switched capacitor circuit of claim 1 , further comprising a first set of switches and a second set of switches, the first set of switches controlled to couple the first capacitor to the second capacitor in the second mode of operation, and the second set of switches controlled to couple the first capacitor to the second capacitor and couple the third capacitor on the first side to the common node of the first capacitor and the second capacitor and on the second side to the current source control voltage in the first mode of operation.

4. The switched capacitor circuit of claim 1 , in which the circuit comprises a high impedance differential circuit.

5. The switched capacitor circuit of claim 1 , further comprising a buffer to charge the third capacitor, and in which the third capacitor is charged between the common mode reference voltage and an applied bias voltage in a previous phase of operation.

6. A phase locked loop (PLL) circuit, comprising:
a first circuit having differential output terminals; and
a switched capacitor circuit comprising:
a first capacitor coupled in series with a second capacitor in a first mode of operation across the differential output terminals of the first circuit, and coupled in an anti-parallel layout in a second mode of operation; and
a third capacitor coupled on a first side to a common node of the first capacitor and the second capacitor and on a second side to a current source control voltage in the first mode of operation, and coupled between a bias reference voltage and a common mode reference voltage in the second mode of operation.

7. The PLL circuit of claim 6 , further comprising a fourth capacitor coupled in series with a fifth capacitor, the fourth capacitor coupled across a first of the differential output terminals of the first circuit and the current source control voltage, the fifth capacitor coupled across a second of the differential output terminals of the first circuit and the current source control voltage.

8. The PLL circuit of claim 6 , further comprising a first set of switches and a second set of switches, the first set of switches controlled to couple the first capacitor to the second capacitor in the second mode of operation, and the second set of switches controlled to couple the first capacitor to the second capacitor and couple the third capacitor on the first side to the common node of the first capacitor and the second capacitor and on the second side to the current source control voltage in the first mode of operation.

9. The PLL circuit of claim 6 , in which the first circuit comprises a high impedance differential circuit.

10. The PLL circuit of claim 6 , further comprising a buffer to charge the third capacitor, and in which the third capacitor is charged between the common mode reference voltage and an applied bias voltage in a previous phase of operation.

11. The PLL circuit of claim 6 , further comprising a delay cell to produce a fixed delay as a fraction of an input clock period.

12. The PLL circuit of claim 11 , in which the fixed delay is based at least in part on a fixed current derived for the switched capacitor circuit.

Assignees

• Qualcomm Inc

Inventors

• Bhatta Debesh
• Hinrichs Jeffrey Mark
• Yin Wenjing

Classifications

• H03L7/0891 Primary

  the up-down pulses controlling source and sink current generators, e.g. a charge pump · CPC title

• H03L7/23

  with pulse counters or frequency dividers · CPC title

• H03G1/0094

  using switched capacitors · CPC title

• H03L7/0896 Primary

  the current generators being controlled by differential up-down pulses · CPC title