Low power operational amplifier trim offset circuitry

Patent metadata

Field	Value
Publication number	US-11558013-B2
Application number	US-201916701629-A
Country	US
Kind code	B2
Filing date	Dec 3, 2019
Priority date	Dec 3, 2019
Publication date	Jan 17, 2023
Grant date	Jan 17, 2023

Abstract

Enhanced operational amplifier trim circuitry and techniques are presented herein. In one implementation, a circuit includes a reference circuit configured to produce a set of reference voltages, and a digital-to-analog conversion (DAC) circuit. The DAC circuit comprises a plurality of transistor pairs, where each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based at least on the set of reference voltages and sizing among transistors of each pair. The circuit also includes drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively couple one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

First claim

What is claimed is:

1. A circuit comprising:
a reference circuit configured to produce a set of reference voltages, the reference circuit comprising one or more bandgap reference elements configured to produce one or more source reference voltages; a sample and hold circuit configured to sample the one or more source reference voltages according to a sample rate and store representations of the one or more source reference voltages for presentation as the set of reference voltages, wherein the one or more bandgap reference elements are decoupled from the sample and hold circuit after each sample of the one or more source reference voltages;
a digital-to-analog conversion (DAC) circuit comprising a plurality of transistor pairs, wherein each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based on the set of reference voltages and sizing among transistors of each pair; and
drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively provide one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

2. The circuit of claim 1 , comprising:
control circuitry configured to selectively apply the digital trim codes during active cycles of the operational amplifier, and selectively couple the one or more bandgap reference elements to the sample and hold circuit during sample times.

3. A circuit comprising:
a reference circuit configured to produce a set of reference voltages;
a digital-to-analog conversion (DAC) circuit comprising a plurality of transistor pairs, wherein each pair among the plurality of transistor pairs is configured to provide portions of adjustment currents for an operational amplifier based on the set of reference voltages and sizing among transistors of each pair, and wherein the set of reference voltages comprises a first reference voltage coupled to first gate terminals of each of the plurality of transistor pairs, and a second reference voltage coupled to second gate terminals of the plurality of transistor pairs; and
drain switching elements coupled to drain terminals of the transistors of each pair and configured to selectively provide one or more of the portions of the adjustment currents to the operational amplifier in accordance with digital trim codes.

4. The circuit of claim 3 , wherein the digital trim codes are applied to gate terminals of the drain switching elements during active cycles of the operational amplifier, and wherein the drain switching elements are inactivated during inactive cycles of the operational amplifier.

5. The circuit of claim 3 , comprising:
the drain switching elements configured to provide the adjustment currents to an input stage of the operational amplifier, wherein pairs of output terminals of the drain switching elements are coupled to form the adjustment currents to adjust imbalances between input transistors of the input stage of the operational amplifier.

6. The circuit of claim 3 , wherein each transistor among the plurality of transistor pairs comprises a source terminal coupled to a current supply, and a drain terminal coupled to two associated drain switching elements, wherein the two associated drain switching elements are controlled by an associated bit position in the digital trim codes.

7. The circuit of claim 3 , wherein the drain switching elements include:
a first set of drain switching elements each coupled between a respective transistor of the plurality of transistor pairs and a first node common to each of the transistors of the plurality of transistor pairs; and
a second set of drain switching elements each coupled between a respective transistor of the plurality of transistor pairs and a second node common to each of the transistors of the plurality of transistor pairs.

8. The circuit of claim 7 further comprising the operational amplifier, wherein the operational amplifier includes:
a current source;
a first input transistor coupled between the current source and the first node; and
a second input transistor coupled between the current source and the second node.

9. The circuit of claim 8 , wherein:
the operational amplifier further includes a first differential input and a second differential input;
the first input transistor includes a gate coupled to the first differential input; and
the second input transistor includes a gate coupled to the second differential input.

10. An operational amplifier trim circuit comprising:
storage elements configured to hold at least two reference voltages produced by a reference circuit;
a plurality of transistor pairs configured to provide a trim current based on the at least two reference voltages and feature sizing among the transistor pairs, wherein each of the plurality of transistor pairs includes a first transistor that includes a first gate coupled to receive a first reference voltage of the at least two reference voltages and a second transistor that includes a second gate coupled to receive a second reference voltage of the at least two reference voltages; and
pairs of switching elements coupled to drain terminals of transistors among the transistor pairs and configured to selectively couple one or more portions of the trim current to an operational amplifier in accordance with a control code.

11. The operational amplifier trim circuit of claim 10 , wherein the first transistor of each of the plurality of transistor pairs is configured to provide a first portion of the trim current of an associated transistor pair, and the second transistor of each of the plurality of transistor pairs is configured to provide a second portion of the trim current of the associated transistor pair.

12. The operational amplifier trim circuit of claim 11 , wherein a first pair of switching elements is coupled to a drain terminal of the first transistor, and a second pair of switching elements is coupled to a drain terminal of the second transistor; and
wherein the first pair of switching elements and the second pair of switching elements selectively provide at least a portion of the trim current as controlled by portions of the control code applied to gate terminals of the first pair of switching elements and the second pair of switching elements.

13. The operational amplifier trim circuit of claim 10 , comprising:
the reference circuit comprising one or more bandgap reference elements configured to produce the at least two reference voltages; and
the storage elements configured to sample the at least two reference voltages and store samples of the at least two reference voltages, wherein the one or more bandgap reference elements are decoupled from the storage elements after each sample of the at least two reference voltages.

14. The operational amplifier trim circuit of claim 13 , comprising:
control circuitry configured to selectively apply the control code during an active cycle of the operational amplifier to gate terminals of the pairs of switching elements, and selectively couple the one or more bandgap reference elements to the storage elements during sample times.

15. The operation amplifier trim circuit of claim 10 , wherein the trim current is formed by selective coupling of ones of the drain terminals of the transistors among the transistor pairs to an input stage of the operational amplifier, wherein the selective coupling occurs according to the control code by pairs of switching elements corresponding to each of the transistor pairs.

16. A method of operating a

Assignees

• Texas Instruments Inc

Inventors

• Agarwal Nitin
• Karanjkar Kunal
• Ramanan Venkata

Classifications

• H03F2203/45044

  One or more switches are opened or closed to balance the dif amp to reduce the offset of the dif amp · CPC title

• H03F3/45995

  using switching means · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03F3/45475 Primary

  using IC blocks as the active amplifying circuit · CPC title

• H03F3/45197

  Pl types (H03F3/45224, H03F3/45251 take precedence) · CPC title