Vertical high-blocking III-V bipolar transistor

Patent metadata

Field	Value
Publication number	US-11557665-B2
Application number	US-202117368279-A
Country	US
Kind code	B2
Filing date	Jul 6, 2021
Priority date	Jul 6, 2020
Publication date	Jan 17, 2023
Grant date	Jan 17, 2023

Abstract

A vertical high-blocking III-V bipolar transistor, which includes an emitter, a base and a collector. The emitter has a highly doped emitter semiconductor contact region of a first conductivity type and a first lattice constant. The base has a low-doped base semiconductor region of a second conductivity type and the first lattice constant. The collector has a layered low-doped collector semiconductor region of the first conductivity type with a layer thickness greater than 10 μm and the first lattice constant. The collector has a layered highly doped collector semiconductor contact region of the first conductivity type. A first metallic connecting contact layer is formed in regions being integrally connected to the emitter. A second metallic connecting contact layer is formed in regions being integrally connected to the base. A third metallic connecting contact region is formed at least in regions being arranged beneath the collector.

First claim

What is claimed is:

1. A vertical high-blocking III-V bipolar transistor comprising:
an emitter comprising a highly doped emitter semiconductor contact region of a first conductivity type with a dopant concentration greater than 1·10 18 cm −3 and a first lattice constant;
a base comprising a low-doped base semiconductor region of a second conductivity type and the first lattice constant, a dopant concentration of the low-doped base semiconductor region being less than 10 17 cm −3 ; and
a collector comprising a layered low-doped collector semiconductor region of the first conductivity type with a layer thickness greater than 10 μm and the first lattice constant,
wherein the collector comprises a layered highly doped collector semiconductor contact region of the first conductivity type with a dopant concentration greater than 1·10 18 cm 3 ,
wherein the base and collector semiconductor regions and the emitter and collector semiconductor contact regions are arranged in the specified sequence,
wherein a first connecting contact layer is integrally connected to the emitter,
wherein a second connecting contact layer is integrally connected to the base,
wherein a third connecting contact layer is arranged beneath the collector, and
wherein the emitter semiconductor contact region, the base semiconductor region and the collector semiconductor region each comprise a III-V material.

2. The vertical III-V bipolar transistor according to claim 1 , wherein the emitter includes a highly doped emitter intermediate layer of the first conductivity type, the emitter intermediate layer being arranged between the emitter semiconductor contact region and the base semiconductor region having a dopant concentration greater than 1·10 18 cm −3 and a first band gap energy, the base semiconductor region having a second band gap energy, and the first band gap energy being greater than the second band gap energy.

3. The vertical III-V bipolar transistor according to claim 1 , wherein the collector includes a collector intermediate layer of the second conductivity type, the collector intermediate layer being arranged between the base semiconductor region and the collector semiconductor region having a dopant concentration less than 5·10 17 cm −3 and a third band gap energy, the base semiconductor region having a second band gap energy, and the third band gap energy being greater than the second band gap energy.

4. The vertical III-V bipolar transistor according to claim 3 , wherein the base semiconductor region comprises GaAs, and the collector intermediate layer comprises InGaP or AlGaAs.

5. The vertical III-V bipolar transistor according to claim 1 , wherein the collector semiconductor contact region is a substrate layer.

6. The vertical III-V bipolar transistor according to claim 1 , wherein the bipolar transistor comprises a semiconductor substrate region, the semiconductor substrate region being arranged between the third connecting contact layer and the collector semiconductor contact region.

7. The vertical III-V bipolar transistor according to claim 1 , wherein the bipolar transistor comprises a metamorphic buffer layer sequence of the first conductivity type, which comprises a layer thickness of more than 0.5 μm and less than 20 μm, the metamorphic buffer layer sequence having an upper side with the first lattice constant and an underside with a second lattice constant, and the metamorphic buffer layer sequence being arranged between the collector semiconductor region and the collector semiconductor contact region or beneath the collector semiconductor contact region or being designed as the collector semiconductor contact region, all semiconductor regions arranged beneath the metamorphic buffer layer sequence having the second lattice constant and the first conductivity type.

8. The vertical III-V bipolar transistor according to claim 1 , wherein the first conductivity type is p and the second conductivity type is n.

9. The vertical III-V bipolar transistor according to claim 1 , wherein at least the emitter is designed as a mesa structure having a first height on a surface of the base.

10. The vertical III-V bipolar transistor according to claim 9 , wherein the bipolar transistor comprises a semiconductor edge region with a width B and a second height H2, the edge region extending along the edge of the surface of the base around the emitter, the first connecting contact layer and the second connecting contact layer, the second height of the semiconductor edge region being less than or equal to the first height of the emitter, and the semiconductor edge region along second height including a material corresponding to the emitter.

11. The vertical III-V bipolar transistor according to claim 1 , wherein the emitter semiconductor contact region, the base semiconductor region and the collector semiconductor region each consists of a III-V material.

12. The vertical III-V bipolar transistor according to claim 1 , wherein the first, second and third connecting contact layers are all metallic.

13. The vertical III-V bipolar transistor according to claim 1 , wherein the first conductivity type is n and the second conductivity type is p.

14. The vertical III-V bipolar transistor according to claim 3 , wherein the base semiconductor region consists of GaAs, and the collector intermediate layer consists of InGaP or AlGaAs.

15. The vertical III-V bipolar transistor according to claim 2 , wherein the bipolar transistor comprises a semiconductor edge region with a width B and a height H2, the semiconductor edge region extending along the edge of the surface of the base around the emitter, the first connecting contact layer and the second connecting contact layer, the height H2 of the semiconductor edge region corresponding to a height of the emitter intermediate layer, and a material of the semiconductor edge region corresponding to a material of the emitter intermediate layer.

16. The vertical III-V bipolar transistor according to claim 1 , further comprising:
a base semiconductor contact region of the second conductivity type with a dopant concentration greater than 1·10 18 cm −3 , the base semiconductor contact region extending from a first partial region of an upper side of the base semiconductor region and extending into the base semiconductor region.

17. The vertical III-V bipolar transistor according to claim 16 , wherein the second connecting contact layer is connected to the base semiconductor contact region.

18. The vertical III-V bipolar transistor according to claim 2 , wherein the base semiconductor region comprises GaAs, and the emitter intermediate layer comprises InGaP or AlGaAs.

19. The vertical III-V bipolar transistor according to claim 2 , wherein the base semiconductor region consists of GaAs, and the emitter intermediate layer consists of InGaP or AlGaAs.

Assignees

• Azur Space Solar Power Gmbh

Inventors

• Keller Gregor
• WAECHTER Clemens
• Fuhrmann Daniel

Classifications

• H01L29/1004

  Electricity · mapped topic

• H01L29/0821

  Electricity · mapped topic

• H01L29/7371 Primary

  Electricity · mapped topic

• H01L29/0817

  Electricity · mapped topic

• H01L29/205

  Electricity · mapped topic