High performance super-beta NPN (SBNPN)

Patent metadata

Field	Value
Publication number	US-10032868-B2
Application number	US-201615261024-A
Country	US
Kind code	B2
Filing date	Sep 9, 2016
Priority date	Sep 9, 2016
Publication date	Jul 24, 2018
Grant date	Jul 24, 2018

Abstract

A method for making a super β NPN (SBNPN) transistor includes depositing a tetraethyl orthosilicate (TEOS) layer on a P type epitaxial layer; depositing a nitride layer on the TEOS layer; patterning an emitter region of the SBNPN transistor by selectively etching away portions of the nitride layer and the TEOS layer; depositing a second TEOS layer on top of the nitride layer, along sides of the nitride layer and the TEOS layer, and on top of the P type epitaxial layer; and implanting the P type epitaxial layer through the second TEOS layer with N type ions to form the emitter region of the SBNPN transistor.

First claim

What is claimed is:

1. A method for making a super β NPN (SBNPN) transistor having a common-emitter current gain of 1000 or more, comprising:
depositing a tetraethyl orthosilicate (TEOS) layer on a P type epitaxial layer;
depositing a nitride layer on the TEOS layer;
patterning an emitter region of the SBNPN transistor by selectively etching away portions of the nitride layer and the TEOS layer;
depositing a second TEOS layer on top of the nitride layer, along sides of the nitride layer and the TEOS layer, and on top of the P type epitaxial layer; and implanting the P type epitaxial layer through the second TEOS layer with N type ions to form the emitter region of the SBNPN transistor.

2. The method of claim 1 , wherein depositing the second TEOS layer comprises filling in undercut regions of the nitride layer and the TEOS layer.

3. The method of claim 1 , wherein depositing the second TEOS layer comprises depositing the second TEOS layer with a low temperature, low deposition rate process.

4. The method of claim 1 , wherein depositing the second TEOS layer comprises depositing a homogenous screen oxide for the implant step.

5. The method of claim 1 , further comprising removing the TEOS layer within the emitter region of the SBNPN transistor before depositing the second TEOS layer.

6. The method of claim 1 , further comprising depositing a layer of photoresist on the second TEOS layer before the implant step.

7. The method of claim 1 , wherein implanting the P type epitaxial layer through the second TEOS layer with N type ions comprises implanting the P type epitaxial layer with arsenic.

8. A method for making a super βNPN (SBNPN) transistor having a common-emitter current gain of 1000 or more, comprising:
depositing a screen oxide layer, a first tetraethyl orthosilicate (TEOS) layer, a nitride layer, and a first photoresist layer on a P type epitaxial layer;
patterning the first photoresist layer to expose an emitter region of the SBNPN transistor,
etching away the screen oxide layer, the first TEOS layer, the nitride layer in the emitter region of the SBNPN transistor;
removing the first photoresist layer;
depositing a second TEOS layer over the nitride layer and over the P type epitaxial layer in the emitter region of the SBNPN transistor;
depositing a second photoresist layer on the second TEOS layer;
patterning the second photoresist layer to expose an emitter implant region of the SBNPN transistor; and
implanting the P type epitaxial layer through the second TEOS layer to form the emitter region of the SBNPN transistor.

9. The method of claim 8 , further comprising removing the second photoresist layer.

10. The method of claim 9 , further comprising etching away the second TEOS layer in the emitter region of the SBNPN transistor.

11. The method of claim 10 , further comprising depositing an emitter polysilicon layer.

12. The method of claim 8 , wherein depositing the second TEOS layer comprises filling in undercut regions of the nitride layer and the first TEOS layer.

13. The method of claim 8 , wherein depositing the second TEOS layer comprises depositing the second TEOS layer with a low temperature, low deposition rate process.

14. The method of claim 8 , wherein depositing the second TEOS layer comprises depositing a homogenous screen oxide for the implant step.

15. A super β NPN (SBNPN) transistor having a common-emitter current gain of 1000 or more, comprising:
a base;
an emitter; and
a collector,
wherein the emitter is formed by:
depositing a first tetraethyl orthosilicate (TEOS) layer on a P type epitaxial layer;
depositing a nitride layer on the first TEOS layer;
patterning an emitter region of the SBNPN transistor by selectively etching away portions of the nitride layer and the first TEOS layer;
depositing a second TEOS layer on top of the nitride layer, along sides of the nitride layer and the first TEOS layer, and on top of the P type epitaxial layer; and
implanting the P type epitaxial layer through the second TEOS layer to form the emitter region of the SBNPN transistor.

16. The SBNPN transistor of claim 15 , wherein the P type epitaxial layer is implanted with N type ions.

17. The SBNPN transistor of claim 16 , wherein the N type ions comprise arsenic.

18. The SBNPN transistor of claim 15 , wherein the second TEOS layer comprises a low temperature, low deposition rate TEOS layer.

19. The SBNPN transistor of claim 15 , wherein the emitter comprises a polysilicon layer.

20. The SBNPN transistor of claim 15 , wherein the emitter comprises a screen oxide layer.

21. A method for making a super β NPN (SBNPN) transistor having a common-emitter current gain of at least 1000, comprising:
depositing a tetraethyl orthosilicate (TEOS) layer on a P type epitaxial layer;
depositing a nitride layer on the TEOS layer;
patterning an emitter region of the SBNPN transistor by selectively etching away portions of the nitride layer and the TEOS layer;
depositing a second TEOS layer on top of the nitride layer, along sides of the nitride layer and the TEOS layer, and on top of the P type epitaxial layer; and
implanting the P type epitaxial layer through the second TEOS layer with N type ions to form the emitter region of the SBNPN transistor.

22. The method of claim 1 , wherein the SBNPN transistor comprises a common-emitter gain that is substantially higher than a standard NPN transistor fabricated in a process technology that is the same as that of the SBNPN transistor.

Assignees

• Texas Instruments Inc

Inventors

• BENNA Bernhard
• Schwartz Wolfgang
• STAUFER Berthold Georg

Classifications

• H10P30/212

  Through-implantation · CPC title

• H10P30/204

  into Group IV semiconductors · CPC title

• H10P30/22

  using masks · CPC title

• H01L29/0804 Primary

  Electricity · mapped topic

• H01L21/2652

  Electricity · mapped topic