Integrated circuit including simple cell interconnection and method of designing the same

Patent metadata

Field	Value
Publication number	US-11557584-B2
Application number	US-202017106787-A
Country	US
Kind code	B2
Filing date	Nov 30, 2020
Priority date	Jun 9, 2020
Publication date	Jan 17, 2023
Grant date	Jan 17, 2023

Abstract

An integrated circuit (IC) includes: a first cell including an input pin and an output pin extending in a first direction; a second cell adjacent to the first cell in the first direction and including an input pin and an output pin extending in the first direction; a first cell isolation layer extending between the first cell and the second cell in a second direction crossing the first direction; and a first wire extending in the first direction, overlapping the first cell isolation layer, and being connected to the output pin of the first cell and the input pin of the second cell, wherein the output pin of the first cell, the input pin of the second cell, and the first wire are formed in a first conductive layer as a first pattern extending in the first direction.

First claim

What is claimed is:

1. An integrated circuit (IC) comprising:
a first cell comprising an input pin and an output pin extending in a first direction;
a second cell adjacent to the first cell in the first direction and comprising an input pin and an output pin extending in the first direction;
a first cell isolation layer extending between the first cell and the second cell in a second direction crossing the first direction; and
a first wire extending in the first direction, overlapping the first cell isolation layer, and connected to the output pin of the first cell and the input pin of the second cell,
wherein the output pin of the first cell, the input pin of the second cell, and the first wire are formed in a first conductive layer as a first pattern extending in the first direction.

2. The IC of claim 1 , further comprising:
a third cell adjacent to the second cell in the first direction and comprising an input pin and an output pin extending in the first direction;
a second cell isolation layer extending between the second cell and the third cell in the second direction; and
a second wire extending in the first direction, overlapping the second cell isolation layer, and connected to the output pin of the second cell and the input pin of the third cell,
wherein the output pin of the second cell, the input pin of the third cell, and the second wire are formed in the first conductive layer as a second pattern extending in the first direction.

3. The IC of claim 2 , wherein the second cell is a flip-flop,
wherein the input pin of the second cell is a data input pin of the flip-flop, and
wherein the output pin of the second cell is a data output pin of the flip-flop.

4. The IC of claim 2 , wherein the first cell isolation layer and the second cell isolation layer are aligned in the second direction, and
wherein the first cell and the second cell are adjacent to each other in the second direction.

5. The IC of claim 2 , wherein the first cell is a flip-flop,
wherein the output pin of the first cell is a data output pin of the flip-flop, and
wherein the second cell is a buffer or a delay cell.

6. The IC of claim 2 , further comprising:
a fourth cell adjacent to the third cell in the first direction and comprising an input pin and an output pin extending in the first direction;
a third cell isolation layer extending in the second direction between the third cell and the fourth cell; and
a third wire extending in the first direction, overlapping the third cell isolation layer, and connected to the output pin of the third cell and the input pin of the fourth cell,
wherein the output pin of the third cell, the input pin of the fourth cell, and the third wire are formed in the first conductive layer as a third pattern extending in the first direction.

7. The IC of claim 6 , wherein the input pin of the first cell, the output pin of the second cell, the input pin of the third cell, and the output pin of the fourth cell are aligned in the first direction, and
wherein the output pin of the first cell, the input pin of the second cell, the output pin of the third cell, and the input pin of the fourth cell are aligned in the first direction.

8. The IC of claim 7 , wherein the first cell, the second cell, the third cell, and the fourth cell have the same specification.

9. The IC of claim 1 , wherein the first cell comprises:
at least one active pattern extending in the first direction;
at least one gate electrode extending in the second direction and intersecting with the at least one active pattern;
a source/drain region on one side of the at least one gate electrode; and
a source/drain contact and/or a source/drain via between the source/drain region and the first pattern.

10. The IC of claim 1 , wherein the second cell comprises:
at least one active pattern extending in the first direction;
at least one gate electrode extending in the second direction and intersecting with the at least one active pattern; and
a gate via between the at least one gate electrode and the first pattern.

11. The IC of claim 1 , wherein the first conductive layer comprises:
at least one pattern connected to a gate via and electrically connected to a gate electrode through the gate via;
at least one pattern connected to a source/drain via and electrically connected to a source/drain region through a source/drain contact and the source/drain via; and
at least one pattern connected to a pattern of a second conductive layer through a via of a first via layer.

12. An integrated circuit (IC) comprising:
a first cell and a second cell, each comprising an input pin and an output pin in a back-end-of-line (BEOL) and having the same specification as each other;
a third cell adjacent to the first cell in a first direction; and
a fourth cell adjacent to the second cell in the first direction,
wherein the output pin of the first cell and an input pin of the third cell, or the input pin of the first cell and an output pin of the third cell are formed in a first conductive layer as a first pattern extending in the first direction,
wherein the output pin of the second cell and an input pin of the fourth cell, or the input pin of the second cell and an output pin of the fourth cell are formed in the first conductive layer as a second pattern extending in the first direction, and
wherein the BEOL of the first cell structurally differs from the BEOL of the second cell.

13. The IC of claim 12 , further comprising:
a fifth cell comprising an input pin and an output pin in the BEOL; and
a sixth cell adjacent to the fifth cell in the first direction,
wherein the input pin of the fifth cell and an output pin of the sixth cell, or the output pin of the fifth cell and an input pin of the sixth cell are formed in the first conductive layer as a third pattern extending in the first direction,
wherein the fifth cell has the same specification as the first cell, and
wherein the BEOL of the fifth cell structurally differs from the BEOL of the first cell and the BEOL of the second cell.

14. The IC of claim 12 , wherein each of the third cell and the fourth cell is a flip-flop,
wherein the input pin and the output pin of the third cell are a data input pin and a data output pin of the flip-flop, respectively, and
wherein the input pin and the output pin of the fourth cell are a data input pin and a data output pin of the flip-flop, respectively.

15. The IC of claim 14 , wherein the first cell is a buffer or a delay cell.

16. The IC of claim 12 , wherein each of the first cell, the second cell, the third cell, and the fourth cell comprises power lines extending in parallel to each other in the first direction in the first conductive layer,
wherein the first pattern is on a first track among a plurality of tracks extending in parallel to each other between the power lines in the first direction, and
wherein the second pattern is on a second track among the plurality of tracks.

17. A method of designing an integrated circuit (IC), the method comprising:
placing a first cell from a cell library based on input data defining the IC;
placing a second cell from the cell library to be adjacent to the first cell in a first direction, based on the input data;
adding a first wire connecting an output pin of the first cell to an input pin of the second cell, based on the input data; and
generating output data defining a layout of the IC,
wherein the output data defines a first pattern extending in the first direction in a first conductive layer and forming the output pin of the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kim Yongcheul
• Kwon Jooyeon
• Park Sangdo

Classifications

• G06F30/392

  Floor-planning or layout, e.g. partitioning or placement · CPC title

• G06F30/3953

  detailed · CPC title

• G06F30/39

  Circuit design at the physical level (physical level design for reconfigurable circuits G06F30/347) · CPC title

• H01L23/528

  Electricity · mapped topic

• H01L27/0924

  Electricity · mapped topic