Microelectronic assemblies having an integrated capacitor

Patent metadata

Field	Value
Publication number	US-11557579-B2
Application number	US-202017129269-A
Country	US
Kind code	B2
Filing date	Dec 21, 2020
Priority date	Dec 27, 2018
Publication date	Jan 17, 2023
Grant date	Jan 17, 2023

Abstract

Microelectronic assemblies, related devices, and methods are disclosed herein. In some embodiments, a microelectronic assembly may include a die having a first surface and an opposing second surface; a capacitor having a surface, wherein the surface of the capacitor is coupled to the first surface of the die; and a conductive pillar coupled to the first surface of the die. In some embodiments, a microelectronic assembly may include a capacitor in a first dielectric layer; a conductive pillar in the first dielectric layer; a first die having a surface in the first dielectric layer; and a second die having a surface in a second dielectric layer, wherein the second dielectric layer is on the first dielectric layer, and wherein the surface of the second die is coupled to the capacitor, to the surface of the first die, and to the conductive pillar.

First claim

The invention claimed is:

1. A microelectronic assembly, comprising:
a multi-layer structure including multiple layers of dielectric material, wherein the multi-layer structure includes one or more conductive pathways through the dielectric material;
an intermediate region including multiple capacitors;
a first die, wherein the intermediate region is between the first die and the multi-layer structure;
a second die, wherein the intermediate region is between the second die and the multi-layer structure; and
a third die, wherein the intermediate region is between the third die and the multi-layer structure;
wherein:
the first die, the second die, and the third die are coupled to the intermediate region,
the second die is between the first die and the third die,
ball grid array interconnects are at a surface of the multi-layer structure such that the multi-layer structure is between the ball grid array interconnects and the intermediate region,
the intermediate region includes conductive structures extending between a bottom surface of the intermediate region and a top surface of the intermediate region,
a plane, parallel to a layer of dielectric material of the multi-layer structure, extends through the capacitors and the conductive structures, and
the intermediate region is coupled to the multi-layer structure.

2. The microelectronic assembly of claim 1 , wherein at least one of the first die, the second die, and the third die includes a processing device.

3. The microelectronic assembly of claim 1 , wherein the conductive structures have a circular cross-section.

4. The microelectronic assembly of claim 1 , wherein the first die, the second die, and the third die are coupled to the intermediate region by solder.

5. The microelectronic assembly of claim 1 , wherein the intermediate region is coupled to the multi-layer structure directly.

6. The microelectronic assembly of claim 1 , wherein the intermediate region is coupled to the multi-layer structure by solder.

7. The microelectronic assembly of claim 1 , wherein a line from the first die to the multi-layer structure, perpendicular to a plane of a layer of dielectric material of the multi-layer structure, passes through the intermediate region.

8. The microelectronic assembly of claim 1 , wherein a line from the second die to the multi-layer structure, perpendicular to a plane of a layer of dielectric material of the multi-layer structure, passes through the intermediate region.

9. The microelectronic assembly of claim 1 , wherein a line from the third die to the multi-layer structure, perpendicular to a plane of a layer of dielectric material of the multi-layer structure, passes through the intermediate region.

10. The microelectronic assembly of claim 1 , wherein a plane, parallel to a layer of dielectric material of the multi-layer structure, extends through the first die, the second die, and the third die.

11. The microelectronic assembly of claim 1 , wherein a line from the first die to the third die, parallel to a plane of a layer of dielectric material of the multi-layer structure, passes through the second die.

12. The microelectronic assembly of claim 1 , wherein the second die is laterally between the first die and the third die.

13. A microelectronic assembly, comprising:
a package substrate;
an intermediate region including multiple capacitors;
a first die, wherein the intermediate region is between the first die and the package substrate;
a second die, wherein the intermediate region is between the second die and the package substrate; and
a third die, wherein the intermediate region is between the third die and the package substrate;
wherein:
the first die, the second die, and the third die are coupled to the intermediate region,
the second die is laterally between the first die and the third die,
ball grid array interconnects are at a surface of the package substrate such that the package substrate is between the ball grid array interconnects and the intermediate region,
the intermediate region includes conductive structures extending between a bottom surface of the intermediate region and a top surface of the intermediate region,
the capacitors are at least partially coplanar with the conductive structures, and
the intermediate region is coupled to the package substrate by solder.

14. The microelectronic assembly of claim 13 , wherein at least one of the first die, the second die, and the third die includes a processing device.

15. The microelectronic assembly of claim 13 , wherein the conductive structures have a circular cross-section.

16. The microelectronic assembly of claim 13 , wherein the first die, the second die, and the third die are coupled to the intermediate region by solder.

17. The microelectronic assembly of claim 13 , wherein the intermediate region is coupled to the package substrate directly.

18. The microelectronic assembly of claim 13 , wherein the intermediate region is coupled to the package substrate by solder.

19. The microelectronic assembly of claim 13 , wherein a line from the first die to the package substrate, perpendicular to a plane of a layer of dielectric material of the package substrate, passes through the intermediate region.

20. The microelectronic assembly of claim 13 , wherein a line from the second die to the package substrate, perpendicular to a plane of a layer of dielectric material of the package substrate, passes through the intermediate region.

21. The microelectronic assembly of claim 13 , wherein a line from the third die to the package substrate, perpendicular to a plane of a layer of dielectric material of the package substrate, passes through the intermediate region.

22. The microelectronic assembly of claim 13 , wherein a plane, parallel to a layer of dielectric material of the package substrate, extends through the first die, the second die, and the third die.

23. The microelectronic assembly of claim 13 , wherein a line from the first die to the third die, parallel to a plane of a layer of dielectric material of the package substrate, passes through the second die.

Assignees

• Intel Corp

Inventors

• Zhang Chong
• Xu Cheng
• Zhao Junnan
• Wang Ying
• Jiao Meizi

Classifications

• H01L23/49811

  Electricity · mapped topic

• H01L2224/1623

  Electricity · mapped topic

• H01L21/568

  Electricity · mapped topic

• H01L28/40

  Electricity · mapped topic

• H01L23/5386

  Electricity · mapped topic