Semiconductor memory devices, memory systems and methods of operating semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-11557332-B2
Application number	US-202117322227-A
Country	US
Kind code	B2
Filing date	May 17, 2021
Priority date	Jun 1, 2018
Publication date	Jan 17, 2023
Grant date	Jan 17, 2023

Abstract

A semiconductor memory device includes a memory cell array, an error correction code (ECC) engine, a refresh control circuit, a scrubbing control circuit and a control logic circuit. The refresh control circuit generates refresh row addresses for refreshing a memory region on memory cell rows in response to a first command received from a memory controller. The scrubbing control circuit counts the refresh row addresses and generates a scrubbing address for performing a scrubbing operation on a first memory cell row of the memory cell rows whenever the scrubbing control circuit counts N refresh row addresses of the refresh row addresses. The ECC engine reads first data corresponding to a first codeword, from at least one sub-page in the first memory cell row, corrects at least one error bit in the first codeword and writes back the corrected first codeword in a corresponding memory location.

First claim

What is claimed is:

1. A method of operating a semiconductor memory device including a memory cell array that includes a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of memory cells, the method comprising:
receiving periodic refresh commands from a memory controller during a period of time;
performing a normal refresh operation without scrubbing for refreshing memory cells included in at least one of the memory cell rows in response to a first refresh command of the periodic refresh commands; and
performing a scrubbing operation on at least one sub-page in a first memory cell row of the memory cell rows in response to a second refresh command of the periodic refresh commands,
wherein the performing of the scrubbing operation includes:
incrementing a scrubbing column address until the scrubbing column address reaches a maximum value based on the second refresh command; and
incrementing a scrubbing row address by one as the scrubbing column address reaches the maximum value.

2. The method of claim 1 , wherein the performing of the scrubbing operation further includes:
reading a first data corresponding to a first codeword from the at least one sub-page in the first memory cell row, the at least one sub-page being designated by the scrubbing column address and the scrubbing row address;
correcting at least one error bit in the first codeword; and
writing back the corrected first codeword in a memory location in which the first data is stored.

3. The method of claim 1 , wherein the scrubbing operation is performed on the at least one sub-page instead of the normal refresh operation to be performed in response to the second refresh command.

4. The method of claim 1 , wherein the scrubbing operation is sequentially performed on a plurality of sub-pages in the first memory cell row.

5. The method of claim 1 , further comprising:
generating weak codeword addresses associated with weak codewords in the memory cell array; and
performing a weak scrubbing operation on the weak codewords.

6. The method of claim 1 , wherein the scrubbing operation is performed once in response to the normal refresh operation being performed N times, and N is a natural number greater than one.

7. A method of operating a semiconductor memory device including a memory cell array that includes a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of memory cells, the method comprising:
generating periodic refresh control signals during a period of time in a self-refresh mode;
performing a normal refresh operation without scrubbing for refreshing memory cells included in at least one of the memory cell rows in response to a first refresh control signal of the periodic refresh control signals; and
performing a scrubbing operation on at least one sub-page in a first memory cell row of the memory cell rows in response to a second refresh control signal of the periodic refresh control signals,
wherein the performing of the scrubbing operation includes:
incrementing a scrubbing column address until the scrubbing column address reaches a maximum value based on the second refresh control signal; and
incrementing a scrubbing row address by one as the scrubbing column address reaches the maximum value.

8. The method of claim 7 , wherein the performing of the scrubbing operation further includes:
reading a first data corresponding to a first codeword from the at least one sub-page in the first memory cell row, the at least one sub-page being designated by the scrubbing column address and the scrubbing row address;
correcting at least one error bit in the first codeword; and
writing back the corrected first codeword in a memory location in which the first data is stored.

9. The method of claim 7 , wherein the scrubbing operation is performed on the at least one sub-page instead of the normal refresh operation to be performed in response to the second refresh control signal.

10. The method of claim 7 , wherein the scrubbing operation is sequentially performed on a plurality of sub-pages in the first memory cell row.

11. The method of claim 7 , further comprising:
generating weak codeword addresses associated with weak codewords in the memory cell array; and
performing a weak scrubbing operation on the weak codewords.

12. The method of claim 7 , wherein the scrubbing operation is performed once in response to the normal refresh operation being performed N times, and N is a natural number greater than one.

13. A method of operating a semiconductor memory device including a memory cell array that includes a plurality of memory cell rows, each of the plurality of memory cell rows including a plurality of memory cells, the method comprising:
generating periodic refresh row addresses during a period of time in a self-refresh mode;
performing a normal refresh operation without scrubbing for refreshing memory cells included in at least one of the memory cell rows in response to a first refresh row address of the periodic refresh row addresses; and
performing a scrubbing operation on at least one sub-page in a first memory cell row of the memory cell rows in response to a second refresh row address of the periodic refresh row addresses.

14. The method of claim 13 , wherein the scrubbing operation is performed on the at least one sub-page instead of the normal refresh operation to be performed in response to the second refresh row address.

15. The method of claim 13 , wherein the performing of the scrubbing operation includes:
generating a scrubbing address including a scrubbing row address and a scrubbing column address based on the second refresh row address;
reading a first data corresponding to a first codeword from the at least one sub-page in the first memory cell row, the at least one sub-page being designated by the scrubbing column address and the scrubbing row address;
correcting at least one error bit in the first codeword; and
writing back the corrected first codeword in a memory location in which the first data is stored.

16. The method of claim 15 , wherein the generating of the scrubbing address includes:
incrementing the scrubbing column address until the scrubbing column address reaches a maximum value based on the second refresh row address; and
incrementing the scrubbing row address by one as the scrubbing column address reaches the maximum value.

17. The method of claim 13 , wherein the scrubbing operation is performed once in response to the normal refresh operation being performed N times, and N is a natural number greater than one.

18. The method of claim 13 , further comprising:
generating weak codeword addresses associated with weak codewords in the memory cell array; and
performing a weak scrubbing operation on the weak codewords.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cha Sang-Uhn
• Kim Hyun-Gi
• Sin Hoon
• Ryu Ye-Sin
• Jun In-Woo

Classifications

• G11C29/4401

  for self repair · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/44

  Indication or identification of errors, e.g. for repair · CPC title

• G06F11/1016

  Error in accessing a memory location, i.e. addressing error · CPC title

• G11C11/40607 Primary

  Refresh operations in memory devices with an internal cache or data buffer · CPC title