Method and apparatus for refreshing and data scrubbing memory device

Patent metadata

Field	Value
Publication number	US-9600362-B2
Application number	US-201514699201-A
Country	US
Kind code	B2
Filing date	Apr 29, 2015
Priority date	Jun 9, 2011
Publication date	Mar 21, 2017
Grant date	Mar 21, 2017

Abstract

At least one refresh without scrubbing is performed on a corresponding portion of the memory device with a first frequency. In addition, at least one refresh with scrubbing is performed on a corresponding portion of the memory device with a second frequency less than the first frequency. Accordingly, refresh operations with data scrubbing are performed to prevent data error accumulation. Furthermore, refresh operations without data scrubbing are also performed to reduce undue power consumption from the data scrubbing.

First claim

What is claimed is:

1. A method of operating a semiconductor memory device, the method comprising:
receiving a first command;
activating a page of a memory array in response to the first command;
selecting at least one sub page from a plurality of sub pages of the activated page from receiving said first command, and wherein at least one sub page of the activated page is not selected from receiving said first command; and
performing a scrubbing operation by detecting an error in data read from the selected sub page and writing error-corrected data back to the selected sub page,
and wherein no error detection operation of said scrubbing operation is performed on said non-selected sub page from receiving said first command.

2. The method of claim 1 , wherein a scrubbing refresh operation is performed in response to the first command, and
the performing of the scrubbing refresh operation includes performing a refresh operation on the activated page and performing the scrubbing operation on the selected sub page.

3. The method of claim 2 , wherein the number of memory cells to be refreshed is different from the number of memory cells to be scrubbed, based on the first command.

4. The method of claim 1 , wherein the first command is a scrubbing refresh command newly defined between a memory controller and the semiconductor memory device.

5. The method of claim 4 , wherein:
the memory array comprises a bank including a plurality of pages, and each page comprises a plurality of sub pages; and
one of the plurality of pages is activated in response to the first command, and data obtained by performing error correction on at least two sub pages of the activated page is written back.

6. The method of claim 5 , wherein the first command is received on a predetermined cycle, and the plurality of pages are sequentially activated every time the first command is received.

7. The method of claim 1 , wherein the first command is a refresh command for a refresh operation of the semiconductor memory device.

8. The method of claim 7 , wherein:
the memory array comprises a bank including a plurality of pages, and each page comprises a plurality of sub pages; and
one of the plurality of pages is activated in response to the refresh command, and data obtained by performing error correction on at least one sub page of the activated page is written back.

9. The method of claim 1 , wherein the operation of writing back is selectively performed when at least one error is detected on data read from the selected sub page.

10. The method of claim 1 , wherein the memory array comprises M pages, each comprising N sub pages,
memory cells of a portion of the N sub pages of each page are scrubbed while memory cells of the M pages are all refreshed, and
memory cells of the N sub pages of each page are all scrubbed while memory cells of the M pages are refreshed at least two times.

11. A semiconductor memory device comprising:
a memory array which comprises a bank including a plurality of pages, each comprising a plurality of sub pages;
a command decoder which decodes an external command to generate an internal command;
an error correction circuit which performs error detection and correction on data read from the memory array; and
a scrubbing refresh management unit which manages execution of an operation of activating a page of the memory array in response to a first command from an external source, selecting at least one sub page from a plurality of sub pages of the activated page from receiving said first command, and wherein at least one sub page of the activated page is not selected from receiving said first command, performing error detection on the selected sub page, and writing error-corrected data back to the sub page, and wherein no error detection operation of said scrubbing operation is performed on said non-selected sub page from receiving said first command.

12. The semiconductor memory device of claim 11 , wherein the scrubbing refresh management unit comprises:
a first counter which performs a counting operation for selecting one of the plurality of pages in response to the first command; and
a second counter which performs a counting operation for selecting one of the plurality of sub pages in response to the first command.

13. The semiconductor memory device of claim 12 , wherein the counting operations of the first and second counters are controlled according to a result of decoding performed on the first command.

14. The semiconductor memory device of claim 11 , wherein the first command is a scrubbing refresh command newly defined between a memory controller and the semiconductor memory device.

15. The semiconductor memory device of claim 11 , wherein the first command is a refresh command for a refresh operation of the semiconductor memory device.

16. A semiconductor memory device comprising:
a memory array;
a command decoder which decodes an external command to generate an internal command;
an error correction circuit which performs error detection and correction on data read from the memory array;
a hard fail detector which receives a result of the error detection and determines whether an error has occurred at least twice in data at the same location on the memory array, to determine existence or non-existence of a hard fail of the memory array; and
an array voltage generator which changes a level of an array voltage which is to be provided to the memory array according to a result of the hard-fail detection.

17. The semiconductor memory device of claim 16 , further comprising a repair logic unit which replaces a defective region of the memory array with a redundant region according to a result of the hard-fail detection.

18. The semiconductor memory device of claim 16 , further comprising a scrubbing refresh management unit which manages execution of an operation of activating a page of the memory array in response to a first command from an external source, selecting at least one sub page from a plurality of sub pages of the activated page, performing error detection on the selected sub page, and writing error-corrected data back to the sub page,
wherein the existence or non-existence of the hard fail is determined based on a result of the error detection performed in response to the first command.

19. The semiconductor memory device of claim 16 , wherein the hard fail detector generates a hold signal for holding an operation of the external controller, when the hard fail is detected.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Kang Uk-Song
• Yu Hak-Soo
• Park Chul-Woo

Classifications

• G11C11/40611 Primary

  External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh · CPC title

• G06F3/0679

  Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP] · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C11/40618

  Refresh operations over multiple banks or interleaving · CPC title