Inverter based on electron interference

Patent metadata

Field	Value
Publication number	US-11552186-B2
Application number	US-202016808420-A
Country	US
Kind code	B2
Filing date	Mar 4, 2020
Priority date	Mar 4, 2020
Publication date	Jan 10, 2023
Grant date	Jan 10, 2023

Abstract

Semiconductor devices includes third arms. A channel from the first and second arms extends to a channel of the third arm. When a current from a first voltage is flowing from the first arm to the second arm, a flow of ballistic electrons is generated that flow through the third arm channel from the channel of the first and second arms to the third arm channel. A fin structure located in the third arm channel and includes a gate. The gate is controlled using a second voltage over the fin structure, the fin structure is formed to induce an energy-field structure that shifts by an amount of the second voltage to control an opening of the gate that the flow of ballistic electrons pass through, which in turn changes a depletion width, subjecting the ballistic electrons to diffraction, and then interference.

First claim

What is claimed is:

1. A semiconductor device, comprising:
an epitaxial layer comprising a III-N heterostructure forming a channel, wherein the III-N heterostructure includes an InAlN/GaN composition formed by an InAlN layer and a GaN layer, wherein a concentration of In in the InAlN layer is tuned to lattice match the InAlN layer with the GaN layer, allowing electron mobility to generate ballistic electrons; and
a fin structure located in the channel,
wherein the fin structure includes a gate formed transversely to a longitudinal axis of the channel, wherein the gate is controllable using a voltage over the fin structure, such that under influence of the voltage, the fin structure induces an energy-field opening a flow of ballistic electrons passing under the gate, which in turn changes a depletion width, subjecting the ballistic electrons to interference, and
wherein the semiconductor device is turned on by applying an amount of the voltage, and turned off by applying no amounts of the voltage.

2. The semiconductor device of claim 1 , further comprising,
at least one metal positioned at a distance from the fin structure from the end of the channel, and positioned at a vertical distance from a center axis, to detect an amount of conductance.

3. A semiconductor inverter, comprising:
an epitaxial layer comprising a III-N heterostructure forming a channel, wherein the III-N heterostructure includes an InAlN/GaN composition formed by an InAlN layer and a GaN layer, wherein a concentration of In in the InAlN layer is tuned to lattice match the InAlN layer with the GaN layer, allowing electron mobility to generate ballistic electrons; and
at least two fin structures located in the channel positioned at a distance from an end of the channel, each fin structure includes
a gate formed transversely to a longitudinal axis of the channel, wherein the gate is controllable using a voltage over the fin structure, such that under influence of the voltage, the fin structure induces an energy-field opening a flow of ballistic electrons passing under the gate, which in turn changes a depletion width, subjecting the ballistic electrons to interference, and

wherein the semiconductor device is turned on by applying an amount of the voltage, and turned off by applying no amounts of the voltage.

4. The semiconductor inverter of claim 3 , further comprising,
at least one metal positioned at a distance from the at least two fin structures from the end of the channel, and positioned at a vertical distance from a center axis, to detect an amount of conductance.

5. A semiconductor device, comprising:
an epitaxial layer comprising a III-N heterostructure forming a channel, wherein the III-N heterostructure includes an InAlN/GaN composition formed by an InAlN layer and a GaN layer, wherein a concentration of In in the InAlN layer is tuned to lattice match the InAlN layer with the GaN layer, allowing electron mobility to generate ballistic electrons;
at least two fin structures located in the channel, each fin structure includes
a gate formed transversely to a longitudinal axis of the channel, wherein the gate is controllable using a voltage over the fin structure, such that under influence of the voltage, the fin structure induces an energy-field opening a flow of ballistic electrons passing under the gate, which in turn changes a depletion width, subjecting the ballistic electrons to diffraction, and then an interference pattern due to a wave nature of the ballistic electrons, such that the interference pattern gives rise to a conductance variation pattern; and
at least one metal positioned at a distance from the at least two fin structures from the end of the channel, and positioned at a vertical distance from a center axis, to detect an amount of conductance,
wherein the semiconductor device is turned on by applying an amount of the voltage, and turned off by applying no amounts of the voltage.

6. The semiconductor device of claim 5 , wherein the detected amount of conductance includes varied orders of magnitude based upon an amount of applied gate bias.

7. A semiconductor device including a structure having a first arm, a second arm and a third arm, such that a channel from the first and second arms extends to a third arm channel of the third arm, wherein the third arm channel provided a flow path for ballistic electrons that are generated by a first voltage between the first arm and the second arm, the semiconductor device comprising:
a first fin structure located in the third arm channel and positioned at a distance from an end of the third arm, wherein the first fin structure includes a first gate formed transversely to a longitudinal axis of the first fin structure, and wherein the first gate is controllable using a second voltage over the fin structure, such that under influence of the second voltage, the first fin structure induces an energy-field opening a flow of the ballistic electrons passing under the first gate, which in turn changes a depletion width, subjecting the ballistic electrons to interference,
wherein the semiconductor device is turned on by applying an amount of the first and the second voltage, and turned off by applying no amounts of the first and the second voltage.

8. The semiconductor device of claim 7 , further comprising,
a second fin structure located in the third arm channel positioned in series with the first fin structure at a same distance as the first fin structure from the end of the third arm, wherein the second fin structure includes a second gate formed transversely to the longitudinal axis of the second fin structure, wherein the second gate is controllable using the second voltage over the second fin structure.

9. The semiconductor device of claim 7 , wherein the first voltage is applied between the first arm and the second arm, such that the first and second arms are configured as a cross shaped structure, to generate the flow of the ballistic electrons.

10. The semiconductor device of claim 9 , wherein a flow velocity of the ballistic electrons is about 2×107 cm·sec-1.

11. The semiconductor device of claim 7 , wherein upon subject to the interference an interference pattern is produced due to a wave nature of electrons, such that the interference pattern gives rise to a conductance variation pattern when the first fin structure is at a location within the distance.

12. The semiconductor device of claim 11 , wherein, at least one metal is positioned at end of the third arm at a vertical position from a center axis of the third arm channel, such that at least one metal is a sensor that is operationally configured to detect an amount of conductance.

13. The semiconductor device of claim 12 , wherein the detected amount of conductance is associated with an order of magnitude, such that the order of magnitude changes depending upon the shifting of the energy-field by a corresponding amount of the second voltage applied to the first fin structure.

14. The semiconductor device of claim 7 , wherein the flow of ballistic electrons is generated by an epitaxial layer that forms the third arm channel, wherein the epitaxial layer includes a III-N heterostructure comprising an InAlN/GaN composition formed by an InAlN layer and a GaN layer, such that a concentration of In in the InAlN layer is tuned to lattice match the InAlN layer with the GaN layer, resulting in electron mobility.

15. The semiconductor device of claim 7 , wherein the first voltage and second voltage are connected to a same ground terminal.

16. The semiconductor device of claim 7 , wherein the first fin structure

Assignees

• Mitsubishi Electric Res Laboratories Inc
• Mitsubishi Electric Res Laboratoriesm Inc

Inventors

• Teo Koon Hoo
• Chowdhurry Nadim

Classifications

• G06F7/388

  using other various devices such as electro-chemical, microwave, surface acoustic wave, neuristor, electron beam switching, resonant, e.g. parametric, ferro-resonant · CPC title

• H03K19/08

  using semiconductor devices (H03K19/173 takes precedence; wherein the semiconductor devices are only diode rectifiers H03K19/12) · CPC title

• B82Y10/00

  Nanotechnology for information processing, storage or transmission, e.g. quantum computing or single electron logic · CPC title

• H01L29/775 Primary

  Electricity · mapped topic

• H01L39/228

  Electricity · mapped topic