Semiconductor package structure and method of making the same

Patent metadata

Field	Value
Publication number	US-11552014-B2
Application number	US-201916676541-A
Country	US
Kind code	B2
Filing date	Nov 7, 2019
Priority date	Nov 16, 2018
Publication date	Jan 10, 2023
Grant date	Jan 10, 2023

Abstract

A semiconductor package structure includes a chip, a conductive pillar, a dielectric layer, a first patterned conductive layer and a second patterned conductive layer. The chip has a first side with at least a first metal electrode pad and a second side with at least a second metal electrode pad. The conductive pillar, which has a first end and a second end, is disposed adjacent to the chip. The axis direction of the conductive pillar is parallel to the height direction of the chip. The dielectric layer covers the chip and the conductive pillar and exposes the first and second metal electrode pads of the chip and the first and second ends of the conductive pillar. The first patterned conductive layer is disposed on a second surface of the dielectric layer and electrically connected between the second metal electrode pad and the second end of the conductive pillar. The second patterned conductive layer is disposed on a first surface of the dielectric layer and electrically connected between the first metal electrode pad and the first end of the conductive pillar.

First claim

What is claimed is:

1. A manufacturing method for a semiconductor package structure, comprising:
providing a carrier;
disposing a temporary bonding layer on a surface of the carrier;
connecting a chip to the temporary bonding layer by its a first side that has a first metal electrode pad;
disposing at least a conductive pillar to the temporary bonding layer by its a first end, and the conductive pillar is also adjacent to the chip;
forming a dielectric layer to cover the chip and the conductive pillar, and exposes at least a second metal electrode pad on a second side of the chip and a second end of the conductive pillar;
forming a first patterned conductive layer to electrically connect the second end of the conductive pillar and the second metal electrode pad of the chip;
removing the temporary bonding layer and the carrier, so as to expose the first side of the chip and the first end of the conductive pillar; and
forming a second patterned conductive layer to electrically connect the first end of the conductive pillar and the first metal electrode pad of the chip.

2. The manufacturing method of claim 1 , further comprising:
forming at least a conductive through-hole, which is arranged between the second metal electrode pad of the chip and the first patterned conductive layer and/or arranged between the first metal electrode pad of the chip and the second patterned conductive layer.

3. The manufacturing method of claim 2 , wherein the chip is a sensor chip with a sensing area on the first side, and the sensing area is exposed on the dielectric layer and the second patterned conductive layer.

4. The manufacturing method of claim 3 , further comprising:
forming a patterned protective layer to cover at least part of the first patterned conductive layer and/or to cover at least part of the second patterned conductive layer and part of the chip, and expose the sensing area of the chip.

5. The manufacturing method of claim 2 , further comprising:
forming a patterned protective layer to cover at least part of the first patterned conductive layer and/or to cover at least part of the second patterned conductive layer and part of the chip.

6. The manufacturing method of claim 1 , wherein the chip is a sensor chip with a sensing area on the first side, and the sensing area is exposed on the dielectric layer and the second patterned conductive layer.

7. The manufacturing method of claim 6 , further comprising:
forming a patterned protective layer to cover at least part of the first patterned conductive layer and/or to cover at least part of the second patterned conductive layer and part of the chip, and expose the sensing area of the chip.

8. The manufacturing method of claim 1 , further comprising:
forming a patterned protective layer to cover at least part of the first patterned conductive layer and/or to cover at least part of the second patterned conductive layer and part of the chip.

9. A manufacturing method for a semiconductor package structure, comprising:
providing a carrier;
disposing a temporary bonding layer on a surface of the carrier;
connecting a chip to the temporary bonding layer by its a first side that has a first metal electrode pad;
disposing at least a conductive pillar to the temporary bonding layer by its a first end, and the conductive pillar is also adjacent to the chip;
forming a dielectric layer to cover the chip and the conductive pillar, and exposes at least a second metal electrode pad on a second side of the chip and a second end of the conductive pillar;
removing the temporary bonding layer and the carrier, so as to expose the first side of the chip and the first end of the conductive pillar;
forming a first patterned conductive layer to electrically connect the second end of the conductive pillar and the second metal electrode pad of the chip;
forming a second patterned conductive layer to electrically connect the first end of the conductive pillar and the first metal electrode pad of the chip; and
wherein the steps of forming the first patterned conductive layer and the second patterned conductive layer are carried out simultaneously.

10. The manufacturing method of claim 9 , further comprising:
forming at least a conductive through-hole, which is arranged between the second metal electrode pad of the chip and the first patterned conductive layer and/or arranged between the first metal electrode pad of the chip and the second patterned conductive layer.

11. The manufacturing method of claim 10 , wherein the chip is a sensor chip with a sensing area on the first side, and the sensing area is exposed on the dielectric layer and the second patterned conductive layer.

12. The manufacturing method of claim 11 , further comprising:
forming a patterned protective layer to cover at least part of the first patterned conductive layer and/or to cover at least part of the second patterned conductive layer and part of the chip, and expose the sensing area of the chip.

13. The manufacturing method of claim 10 , further comprising:
forming a patterned protective layer to cover at least part of the first patterned conductive layer and/or to cover at least part of the second patterned conductive layer and part of the chip.

14. The manufacturing method of claim 9 , wherein the chip is a sensor chip with a sensing area on the first side, and the sensing area is exposed on the dielectric layer and the second patterned conductive layer.

15. The manufacturing method of claim 14 , further comprising:
forming a patterned protective layer to cover at least part of the first patterned conductive layer and/or to cover at least part of the second patterned conductive layer and part of the chip, and expose the sensing area of the chip.

16. The manufacturing method of claim 9 , further comprising:
forming a patterned protective layer to cover at least part of the first patterned conductive layer and/or to cover at least part of the second patterned conductive layer and part of the chip.

Assignees

• Phoenix Pioneer Technology Co Ltd

Inventors

• Hsu Che-Wei
• Hsu Shih-Ping
• Tseng Chao-Tsung

Classifications

• H10W90/00

  Package configurations · CPC title

• H10W70/6523

  for connecting to pads at different heights at the same side of the package substrate, interposer or RDL · CPC title

• H10W70/093

  Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title