Asymmetric cored integrated circuit package supports

Patent metadata

Field	Value
Publication number	US-11552008-B2
Application number	US-201816202690-A
Country	US
Kind code	B2
Filing date	Nov 28, 2018
Priority date	Nov 28, 2018
Publication date	Jan 10, 2023
Grant date	Jan 10, 2023

Abstract

Disclosed herein are asymmetric cored integrated circuit (IC) package supports, and related devices and methods. For example, in some embodiments, an IC package support may include a core region having a first face and an opposing second face, a first buildup region at the first face of the core region, and a second buildup region at the second face of the core region. A thickness of the first buildup region may be different than a thickness of the second buildup region. In some embodiments, an inductor may be included in the core region.

First claim

The invention claimed is:

1. An integrated circuit (IC) package support, comprising:
a core region having a first face and an opposing second face and comprising an inductor between the first face and the second face;
a first buildup region at the first face of the core region; and
a second buildup region at the second face of the core region,
wherein:
a thickness of the first buildup region is different than a thickness of the second buildup region,
the inductor comprises a central solenoid surrounded laterally by a magnetic material,
the first buildup region comprises a first number of layers of a dielectric material,
the second buildup region comprises a second number of layers of the dielectric material, and

the first number is different than the second number.

2. The IC package support of claim 1 , wherein:
the core region includes a first dielectric material,
the dielectric material of the first buildup region is a second dielectric material, and
the first dielectric material has a different material composition than a material composition of the second dielectric material.

3. The IC package support of claim 2 , wherein the first dielectric material includes glass.

4. The IC package support of claim 2 , wherein the first dielectric material includes a prepreg fiber glass material.

5. The IC package support of claim 2 , wherein the second dielectric material includes a resin.

6. The IC package support of claim 1 , further comprising:
conductive contacts for first-level interconnects at a face of the first buildup region; and
conductive contacts for second-level interconnects at a face of the second buildup region.

7. The IC package support of claim 1 , wherein the solenoid comprises stacks of conductive vias in another dielectric material.

8. The IC package support of claim 1 , wherein the core region includes a first core region and a second core region, the second core region is between the first core region and the second buildup region, and the first core region is symmetric about a plane parallel to the first face and the second face.

9. The IC package support of claim 8 , wherein the second core region includes one or more layers of a prepreg fiber glass material.

10. The IC package support of claim 1 , wherein the IC package support is a package substrate or an interposer.

11. The IC package support of claim 1 , wherein the core region has a thickness between 100 microns and 1000 microns.

12. An integrated circuit (IC) package, comprising:
an IC package support having a core, wherein:
the IC package support includes a first buildup region including a first number of buildup layers of a dielectric material at one face of the core,
the IC package support includes a second buildup region including a second number of buildup layers of the dielectric material at an opposite face of the core, and
the first number is different than the second number,
the core comprises an inductor between the one face and the opposite face, and
the inductor comprises a central solenoid surrounded laterally by a magnetic material; and

a die coupled to the IC package support.

13. The IC package of claim 12 , wherein the die includes a processing device.

14. The IC package of claim 12 , wherein the inductor is at least partially embedded in the core.

15. The IC package of claim 14 , wherein the inductor includes the solenoid and the magnetic material proximate to the solenoid.

16. The IC package of claim 15 , wherein the solenoid includes a stack of multiple conductive vias in the core.

17. The IC package of claim 15 , wherein the solenoid includes a via that extends from one face of the core to an other face of the core.

18. The IC package of claim 12 , wherein the IC package support is a package substrate or an interposer.

19. A method of manufacturing an electronic device, comprising:
forming an assembly by attaching a die to a face of an IC package support, wherein:
the IC package support includes a core between a first buildup region and a second buildup region,
the core includes an inductor between the first buildup region and the second buildup region,
the inductor comprises a central solenoid surrounded laterally by a magnetic material,
the first buildup region and the second buildup region have different thicknesses,
the first buildup region comprises a first number of layers of a dielectric material,
the second buildup region comprises a second number of layers of the dielectric material, and
the first number is different than the second number; and

attaching a thermal management device to the assembly.

20. The method of claim 19 , wherein the thermal management device includes a heat sink or a heat spreader.

21. The method of claim 19 , wherein one of the first buildup region and the second buildup region is thicker than the other of the first buildup region and the second buildup region, and the die is attached to conductive contacts of the thicker buildup region.

22. A computing device, comprising:
a circuit board; and
an integrated circuit (IC) package coupled to the circuit board, wherein the IC package includes an IC package support and a computing component coupled to the IC package support, and the IC package support includes:
a core having a first face and an opposing second face, an inductor between the first face and the second face, a first buildup region at the first face of the core, and a second buildup region at the second face of the core,
wherein:
the inductor comprises a central solenoid surrounded laterally by a magnetic material,
a thickness of the first buildup region is different than a thickness of the second buildup region,
the first buildup region comprises a first number of layers of a dielectric material,
the second buildup region comprises a second number of layers of the dielectric material, and

the first number is different than the second number.

23. The computing device of claim 22 , wherein the circuit board is a motherboard.

24. The computing device of claim 22 , wherein the computing device is a handheld computing device or a server computing device.

Assignees

• Intel Corp

Inventors

• Link Lauren Ashley
• Brown Andrew James
• Chatterjee Prithwish
• Vadlamani Sai
• Wang Ying
• Zhang Chong

Classifications

• H05K3/0097

  Processing two or more printed circuits simultaneously, e.g. made from a common substrate, or temporarily stacked circuit boards (H05K3/0052 takes precedence) · CPC title

• H05K3/4682

  Manufacture of core-less build-up multilayer circuits on a temporary carrier or on a metal foil · CPC title

• H05K2203/1536

  Temporarily stacked PCBs · CPC title

• H10W70/692

  Ceramics or glasses · CPC title

• H10W44/501

  Inductive arrangements (H10W44/20 takes precedence) · CPC title