Semiconductor package structure and semiconductor manufacturing process

Patent metadata

Field	Value
Publication number	US-2016233292-A1
Application number	US-201514618822-A
Country	US
Kind code	A1
Filing date	Feb 10, 2015
Priority date	Feb 10, 2015
Publication date	Aug 11, 2016
Grant date	—

Abstract

The present disclosure relates to a semiconductor package structure and a manufacturing method thereof. The semiconductor package structure comprises a first dielectric layer, a die pad, an active component, at least one first metal bar, at least one second metal bar and a through via. The first dielectric layer has a first surface and a second surface opposite to the first surface. The die pad is located within the first dielectric layer. The active component is located within the first dielectric layer and disposed on the die pad. The first metal bar is disposed on the first surface of the first dielectric layer, and electrically connected to the active component. The second metal bar is disposed on the second surface of the first dielectric layer. The through via penetrates the first dielectric layer and connects the at least one first metal bar to the at least one second metal bar.

First claim

1 . A semiconductor package structure, comprising:
a first dielectric layer having a first surface and a second surface opposite to the first surface; a die pad within the first dielectric layer; an active component within the first dielectric layer and disposed on the die pad; a plurality of first metal bars disposed on the first surface of the first dielectric layer, the plurality of first metal bars being substantially parallel to each other, and at least one of the plurality of first metal bars being electrically connected to the active component; a plurality of second metal bars disposed on the second surface of the first dielectric layer, the plurality of second metal bars being substantially parallel to each other; and a plurality of through vias penetrating the first dielectric layer and connecting each of the plurality of first metal bars to a corresponding second metal bar.

2 . The semiconductor package structure of claim 1 , wherein the plurality of first metal bars, the plurality of second metal bars and the plurality of through vias together form an inductor.

3 . The semiconductor package structure of claim 1 , wherein the plurality of first metal bars are not parallel to the plurality of second metal bars.

4 . The semiconductor package structure of claim 1 , wherein
each of the plurality of first metal bars is arranged in a first direction; each of the plurality of second metal bars is arranged in a second direction; and the first direction is different from the second direction.

5 . The semiconductor package structure of claim 1 , further comprising a plurality of leads within the first dielectric layer.

6 . The semiconductor package structure of claim 5 , further comprising:
a first set of metal contacts being disposed on the first surface of the first dielectric layer and electrically connected to the plurality of leads; a first set of vias within the first dielectric layer and electrically connecting the first set of metal contacts to the active component.

7 . The semiconductor package structure of claim 1 , wherein
each through via has a downward-tapering upper portion and an upward-tapering bottom portion, and wherein a depth of the downward-tapering upper portion is different from a depth of the upward-tapering bottom portion.

8 . The semiconductor package structure of claim 1 , further comprising
a core surrounded by the plurality of through vias, wherein the core comprises a magnetic material.

9 . A semiconductor package structure, comprising:
a first dielectric layer having a top surface; a die within the first dielectric layer; and a first spiral inductor within the first dielectric layer, at least one terminal of the first spiral inductor being electrically connected to the die, wherein a central axis of the first spiral inductor is substantially parallel to the top surface of the first dielectric layer.

10 . The semiconductor package structure of claim 9 , wherein the first spiral inductor is arranged at a periphery of the die.

11 . The semiconductor package structure of claim 9 , wherein
the first spiral inductor has a first portion and a second portion, the first portion is exposed from the top surface of the first dielectric layer, and the second portion is exposed from the bottom surface of the first dielectric layer.

12 . The semiconductor package structure of claim 11 , further comprising
a second dielectric layer disposed on the top surface of the first dielectric layer and covering the first set of metal contacts and the first portion of the first spiral inductor.

13 . The semiconductor package structure of claim 12 , further comprising:
a second set of metal contacts disposed on a top surface of the second dielectric layer; and a second set of vias within the second dielectric layer and electrically connecting the second set of metal contacts to one or more of the first set of metal contacts.

14 . The semiconductor package structure of claim 9 , further comprising a second spiral inductor electrically connected to the die.

15 . The semiconductor package structure of claim 9 , further comprising:
a metal layer disposed on the bottom surface of the first dielectric layer; and a third set of vias connecting the metal layer to the die pad.

16 . The semiconductor package structure of claim 9 , further comprising a core surrounded by the first spiral inductor, wherein the core comprises magnetic material.

17 . A method of manufacturing a semiconductor package structure, comprising:
(a) providing a die pad; (b) placing an active component on the die pad; (c) forming a first dielectric layer to encapsulate the die pad and the active component, the first dielectric layer having a first surface and a second surface opposite the first surface; (d) forming a plurality of through vias in the first dielectric material, the plurality of through vias exposed from the first surface and the second surface of the first dielectric layer; (e) forming a first set of metal bars on the first surface of the first dielectric layer to connect to the plurality of through vias; and (f) forming a second set of metal bars on the second surface of the first dielectric layer to connect to the plurality of through vias.

18 . The method of claim 17 , wherein forming a plurality of through vias in (d) further comprises:
forming a plurality of first openings from the first surface of the first dielectric layer without penetrating through to the second surface of the first dielectric layer; plating a metal in the first openings to form first conductive vias; forming a plurality of second openings from the second surface of the first dielectric layer to expose the first conductive vias; plating a metal in the second openings to form second conductive vias, the second conductive vias connecting to the first conductive vias in the first dielectric layer.

19 . The method of claim 17 , wherein
each of the first set of metal bars is arranged in a first direction; each of the second set of metal bars is arranged in a second direction; and the first direction is different from the second direction.

20 . The method of claim 17 , further comprising:
forming a first set of vias within the first dielectric layer to electrically connect to the active component; and forming a first set of metal contacts on the first surface of the first dielectric layer to electrically connect to the first set of vias.

Assignees

• Advanced Semiconductor Eng

Inventors

• Chen Chi-Han

Classifications

• H10W72/0198

  batch processes · CPC title

• H10W72/075

  of bond wires · CPC title

• H10W70/099

  Connecting interconnections to insulating or insulated package substrates, interposers or redistribution layers · CPC title

• H10W72/073

  of die-attach connectors · CPC title

• H10W72/884

  Die-attach connectors and bond wires · CPC title