Secure processor and a program for a secure processor

Patent metadata

Field	Value
Publication number	US-11550962-B2
Application number	US-202016867911-A
Country	US
Kind code	B2
Filing date	May 6, 2020
Priority date	Jun 30, 2004
Publication date	Jan 10, 2023
Grant date	Jan 10, 2023

Abstract

The instruction code including an instruction code stored in the area where the encrypted instruction code is stored in a non-rewritable format is authenticated using a specific key which is specific to the core where the instruction code is executed or an authenticated key by a specific key to perform an encryption processing for the input and output data between the core and the outside.

First claim

The invention claimed is:

1. A processor comprising:
a first execution unit configured to perform a first operation in which an access to a secure address space is permitted;
a second execution unit configured to perform a second operation in which an access to the secure address space is prohibited; and
a memory access control unit configured to access a physical address corresponding to a virtual address by referring to a flag of a page table entry in a translation look-aside buffer,
wherein, only when the first execution unit outputs the virtual address, the memory access control unit permits an access to the physical address within the secure address space in which the flag of the page table entry is set to a value indicating that a corresponding address space is secure, and
wherein, by executing a first instruction code stored in the secure address space by the first execution unit, a second instruction code is checked by the first execution unit before the second instruction code is executed by the second execution unit.

2. The processor according to claim 1 ,
wherein the first instruction code is stored in a non-rewritable memory.

3. The processor according to claim 1 ,
wherein the page table entry further includes a virtual address, a physical address corresponding to the virtual address, and an identifier that indicates secure context.

4. The processor according to claim 1 ,
wherein the second instruction code is executed by the second execution unit after the second instruction code is checked.

5. The processor according to claim 1 ,
wherein the first execution unit is a secure core which includes a code authentication processing block and performs a secure operation including an authentication processing of the second instruction code and the second execution unit is a normal core which perform a normal operation.

6. The processor according to claim 1 ,
wherein the memory access control unit further includes a cache memory containing at least a tag and data corresponding to the tag, and the data is directly returned to the first execution unit without accessing outside of the memory access control unit when cache is hit.

Assignees

• Socionext Inc

Inventors

• Goto Seiji
• Kamada Jun
• Tamiya Taiji

Classifications

• G06F21/71

  to assure secure computing or processing of information · CPC title

• G06F21/52 Primary

  during program execution, e.g. stack integrity {; Preventing unwanted data erasure; Buffer overflow} · CPC title

• G06F21/575

  Secure boot · CPC title

• G06F21/70

  Protecting specific internal or peripheral components, in which the protection of a component leads to protection of the entire computer · CPC title

• G06F21/554

  involving event detection and direct action · CPC title