Serial data interface with reduced loop delay

Patent metadata

Field	Value
Publication number	US-11550749-B2
Application number	US-202117143679-A
Country	US
Kind code	B2
Filing date	Jan 7, 2021
Priority date	Feb 11, 2020
Publication date	Jan 10, 2023
Grant date	Jan 10, 2023

Abstract

A serial peripheral interface (SPI) device includes a serial clock (SCK) pad receiving a serial clock, first and second Schmitt triggers directly electrically connected to the SCK pad to selectively respectively generate first and second clocks in response to rising and falling edges of the serial clock, first and second flip flops clocked by the first and second clocks to output bits of data to a data node, a multiplexer having an input coupled to the data node and an output coupled to driving circuitry, and driving circuitry transmitting data via a master-in-slave-out (MISO) pad.

First claim

The invention claimed is:

1. A slave device for communication with a master device over a serial data bus, the slave device comprising:
a serial clock input pad configured to receive a serial clock;
data sampling circuitry directly electrically connected to the serial clock input pad, and operated by the serial clock to sample output data at each rising and falling edge of the serial clock, and to output the sampled output data to a digital circuit, wherein the data sampling circuitry comprises:
a first Schmitt trigger configured to selectively generate a first clock pulse in response to a rising edge of the serial clock;
a first flip flop clocked by the first clock pulse from the first Schmitt trigger and configured to receive the output data;
a second Schmitt trigger configured to selectively generate a second clock pulse in response to a falling edge of the serial clock; and
a second flip flop clocked by the second clock pulse from the second Schmitt trigger and configured to receive the output data;
wherein outputs of the first and second flip flops are coupled at a node to produce the sampled output data to be output to the digital circuit; and

driving circuitry configured to receive the sampled output data from the digital circuit and to output previously received sampled output data to the master device via a data output pad.

2. The slave device of claim 1 , further comprising a level shifter level configured to shift input data received from the master device via a data input pad from a lower voltage domain to a higher voltage domain; and wherein the output data is based upon the input data.

3. The slave device of claim 1 , further comprising a multiplexer configured to receive input from the outputs of the first and second Schmitt triggers and provide output to a level shifter that shifts the output of the multiplexer from a higher voltage domain to a lower voltage domain to produce a clock signal to be routed to core circuitry.

4. The slave device of claim 3 , further comprising logic circuitry configured to generate a control signal for the first Schmitt trigger, the second Schmitt trigger, and the multiplexer, from control signals defining a form of the serial clock.

5. The slave device of claim 1 , further comprising logic circuitry configured to generate a control signal for the first and second Schmitt triggers, from control signals defining a form of the serial clock.

6. The slave device of claim 1 , wherein the digital circuit receiving the sampled output data from the data sampling circuitry comprises a multiplexer.

7. The slave device of claim 1 , wherein the direct electrical connection from the serial clock input pad to the data sampling circuitry is routed through core circuitry, and back into an input output ring, to the data sampling circuitry.

8. The slave device of claim 1 , wherein the direct electrical connection from the serial clock input pad to the data sampling circuitry is routed solely through an input output ring.

9. The slave device of claim 1 , further comprising a Schmitt trigger configured to receive the serial clock, and a level shifter configured to shift output from the Schmitt trigger from a higher voltage domain to a lower voltage domain to produce a clock signal to be routed to core circuitry.

10. The slave device of claim 1 , wherein the slave device operates according to a Serial Peripheral Interface (SPI) standard.

11. A slave device for communication with a master device over a serial data bus, the slave device comprising:
a serial clock input pad configured to receive a serial clock;
data sampling circuitry directly electrically connected to the serial clock input pad, and operated by the serial clock to sample output data at each rising and falling edge of the serial clock, and to output the sampled output data to a digital circuit, wherein the data sampling circuitry comprises:
a first clock pulse generator configured to selectively generate a first clock pulse in response to a rising edge of the serial clock;
a first storage element clocked by the first clock pulse from the first clock pulse generator and configured to receive the output data;
a second clock pulse generator configured to selectively generate a second clock pulse in response to a falling edge of the serial clock; and
a second storage element clocked by the second clock pulse from the second clock pulse generator and configured to receive the output data;
wherein outputs of the first and second storage elements are coupled at a node to produce the sampled output data to be output to the digital circuit; and

driving circuitry configured to receive the sampled output data from the digital circuit and to output previously received sampled output data to the master device via a data output pad.

12. The slave device of claim 11 , wherein:
the first clock pulse generator is further configured to generate an inverse of its clock pulse in response to the rising edge of the serial clock;
the first storage element is also clocked by the inverse of the clock pulse from the first clock pulse generator;
the second clock pulse generator is further configured to generate an inverse of its clock pulse in response to the falling edge of the serial clock; and
the second storage element is also clocked by the inverse of the clock pulse from the second clock pulse generator.

13. The slave device of claim 11 , further comprising logic circuitry configured to generate an enable signal from a clock phase signal and a clock polarity signal; and wherein the first clock pulse generator, the first storage element, the second clock pulse generator, and the second storage element are enabled by the enable signal.

14. A slave device for communication with a master device using a Serial Peripheral Interface (SPI) standard, the slave device comprising:
a serial clock input (SCK) pad receiving a serial clock from the master device;
a master-out-slave-in (MOSI) pad receiving data from the master device;
a level shifter shifting data received from the master device via the MOSI pad from a lower voltage domain to a higher voltage domain;
a first Schmitt trigger directly electrically connected to the SCK pad to receive the serial clock and generate a first clock in response to a rising edge of the serial clock;
a first flip flop receiving output data and being clocked by the first clock to output a bit of data to a data node;
a second Schmitt trigger directly electrically connected to the SCK pad to receive the serial clock and generate a second clock in response to a falling edge of the serial clock;
a second flip flop receiving output data and being clocked by the second clock to output a bit of data to the data node; and
driving circuitry being coupled to a master-in-slave-out (MISO) pad and transmitting data from the data node to the master device via the MISO pad.

15. The slave device of claim 14 , wherein the direct electrical connection from the SCK input pad to the first and second Schmitt triggers is routed through core circuitry, and back into an input output ring to the first and second Schmitt triggers.

16. The slave device of claim 14 , wherein the direct electrical connection from the serial clock input pad to the first and second Schmitt triggers is routed solely through an input output ring.

17. The slave device of claim 14 , further comprising logic circuitry configured to generate a control signal for the first and second Schmitt triggers, from control signals defining a form of the serial clock.

18. The slave device of claim 1

Assignees

• St Microelectronics Int Nv
• St Microelectronics Rousset

Inventors

• Kumar Manoj
• Kumar Kailash
• Demange Nicolas

Classifications

• G06F13/4282

  on a serial bus, e.g. I2C bus, SPI bus (on daisy chain buses G06F13/4247) · CPC title

• G06F1/06

  Clock generators producing several clock signals {(G06F1/08 - G06F1/14 take precedence)} · CPC title

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• H03K3/3565 Primary

  Bistables with hysteresis, e.g. Schmitt trigger · CPC title