Slave device for a serial synchronous full duplex bus system

Patent metadata

Field	Value
Publication number	US-9916278-B2
Application number	US-201514848472-A
Country	US
Kind code	B2
Filing date	Sep 9, 2015
Priority date	Sep 9, 2014
Publication date	Mar 13, 2018
Grant date	Mar 13, 2018

Abstract

A slave device for a serial synchronous full duplex bus system, which has a data input stage, a clock input stage, an interface logic, a synchronization delay flip-flop, and a data output stage. The slave device is manufactured using nanometer technologies. Also, a method for operating the slave device.

First claim

The invention claimed is:

1. A slave device for a serial synchronous full duplex bus system, the slave device comprising:
a data input stage configured to receive a medium voltage data bus signal from a master device of the bus system and configured to provide a medium voltage data signal, wherein the medium voltage data signal is supplied to a data signal level down shifter configured to produce a low voltage data signal corresponding to the medium voltage data signal;
a clock input stage configured to receive a medium voltage clock bus signal from the master device of the bus system and configured to provide a medium voltage clock signal, wherein the medium voltage clock signal is supplied to a clock signal level down shifter configured to produce a low voltage clock signal corresponding to the medium voltage clock signal;
an interface logic configured to receive the low voltage data signal and the low voltage clock signal and to carry out one or more logical operations in order to produce one or more low voltage output data signals based on the low voltage data signal and based on the low voltage clock signal, the interface logic including a register, wherein, in a second mode of operation, the interface logic is configured to:
receive a bit sequence within the low voltage data signal, which corresponds to a register address of the register;
output, before a last bit of the bit sequence is received, a first low voltage output data signal corresponding to the register address containing the bit sequence without the last bit of the bit sequence and a last bit being set to zero and a second low voltage output data signal corresponding to the register address containing the bit sequence without the last bit of the bit sequence and a last bit being set to one; and
output, after receiving the last bit of the bit sequence, a low voltage address signal containing the last bit;

a selection controller configured to produce a selection output signal depending on the first low voltage output data signal, the second low voltage output data signal, the medium voltage data signal, the low voltage address signal and the medium voltage clock signal;
a synchronization delay flip-flop having a delay flip-flop data input, a delay flip-flop clock input and a delay flip-flop data output, wherein an asynchronous medium voltage output data signal, which is based on the one or more low voltage output data signals, is supplied to the delay flip-flop data input, wherein a medium voltage output clock signal derived from the medium voltage clock bus signal in a medium voltage portion of the slave device is supplied to the delay flip-flop clock input and wherein the delay flip-flop data output provides a synchronous medium voltage output data signal; and
a data output stage configured to transmit a medium voltage data bus signal to the master device of the bus system, wherein the synchronous medium voltage output signal is supplied to the data output stage.

2. The slave device according to claim 1 , wherein the medium voltage output clock signal is the medium voltage clock bus signal or the medium voltage clock signal.

3. The slave device according to claim 1 , wherein the asynchronous medium voltage output data signal is produced by an output data signal up shifter to which the low voltage output data signal or a signal derived from the low voltage output data signal in a low voltage portion of the slave device is supplied to.

4. The slave device according to claim 1 , wherein, in a first mode of operation, the synchronization delay flip-flop is configured to operate in a transparent mode at a beginning of a bus frame and to switch to operate in an edge triggered mode at the arrival of a first edge of the medium voltage output clock signal for the bus frame.

5. The slave device according to claim 1 , wherein the selection controller comprises:
an output producer configured to produce the selection output signal depending on the first low voltage output data signal and the second low voltage output data signal, and
a selection control timer configured to provide a selection control signal for the output producer, which depends on the low voltage address signal, the medium voltage data signal and the medium voltage clock signal.

6. The slave device according to claim 5 , wherein the selection controller comprises an address delay flip-flop comprising an address delay flip-flop data output, an address delay flip-flop clock input and an address delay flip-flop data input, the address delay flip-flop providing the selection control signal at the address delay flip-flop data output depending on the medium voltage data signal and a timing control signal being provided at an address delay flip-flop clock input by an AND gate depending on the low voltage address signal and the medium voltage clock signal.

7. The slave device according to claim 6 , wherein:
the first low voltage output data signal is supplied to a first data signal up shifter configured to produce a first medium voltage output data signal,
the first medium voltage output data signal is supplied to the output producer,
the second low voltage output data signal is supplied to a second data signal up shifter configured to produce a second medium voltage output data signal,
the second medium voltage output data signal is supplied to the output producer,
the medium voltage data signal or the medium voltage data bus signal is supplied to the address delay flip-flop data input,
the low voltage address signal is supplied to an address signal up shifter configured to produce a medium voltage address signal,
the medium voltage address signal is supplied to the AND gate,
the medium voltage clock signal or the medium voltage clock bus signal is supplied to the AND gate,
the selection output signal is a medium voltage selection output signal, and
the medium voltage selection output signal is used as the asynchronous medium voltage output data signal.

8. The slave device according to claim 7 , wherein:
the first low voltage output data signal and the second low voltage output data signal are supplied to the output producer,
the low voltage data signal is supplied to the address delay flip-flop data input,
the low voltage address signal and the low voltage clock signal are supplied to the AND gate,
the selection output signal is a low voltage selection output signal, and
the low voltage selection output signal is used as the low voltage output data signal.

9. The slave device according to claim 1 , wherein the interface logic is configured to, in a third mode of operation:
sequentially receive a plurality of bit sequences within the low voltage data signal, each bit sequence corresponding to a register address of the register,
output a first low voltage output data signal corresponding to a first register address and a second low voltage output data signal corresponding in a time-shared way, and
output a low voltage address signal.

10. A method for operating a slave device for a serial synchronous full duplex bus system, the method comprising:
receiving a medium voltage data bus signal from a master device of the bus system and providing a medium voltage data signal using a data input stage, wherein the medium voltage data signal is supplied to a data signal level down shifter configured to produce a low voltage data signal corresponding to the medium voltage data signal;
receiving a medium voltage clock bus signal from the master device of the bus system and providing a medium voltage clock signal using a clock input stage, wherein the medium voltage clock signal is supplied to a clock signal level down shifter configured to produce a low voltage clock signal corresp

Assignees

• Infineon Technologies Ag

Inventors

• Missoni Albert
• Pichler Matthias

Classifications

• G06F13/4291 Primary

  using a clocked protocol · CPC title

• G06F1/12

  Synchronisation of different clock signals {provided by a plurality of clock generators} · CPC title

• G06F13/364

  using independent requests or grants, e.g. using separated request and grant lines · CPC title

• H04L5/14

  Two-way operation using the same type of signal, i.e. duplex · CPC title

• G06F1/3296

  by lowering the supply or operating voltage · CPC title