Storage system and method for storing logical-to-physical address table entries in a codeword in volatile memory

Patent metadata

Field	Value
Publication number	US-11550658-B1
Application number	US-202117465165-A
Country	US
Kind code	B1
Filing date	Sep 2, 2021
Priority date	Sep 2, 2021
Publication date	Jan 10, 2023
Grant date	Jan 10, 2023

Abstract

A storage system caches logical-to-physical address table entries read in volatile memory. The logical-to-physical address table entries are stored in codewords. The storage system can vary a number or size of an entry in a codeword. Additionally or alternatively, each codeword can store both complete and partial logical-to-physical address table entries. In one example, a codeword having 62 bytes of data and two bytes of error correction code stores 15 complete logical-to-physical address table entries and one partial logical-to-physical address table entry, where the remainder of the partial entry is stored in another codeword. This configuration strikes a good balance between storage space efficiency and random-access write performance.

First claim

What is claimed is:

1. A storage system comprising:
a non-volatile memory;
a volatile memory; and
means for storing first and second codewords in the volatile memory, each of the first and second codewords comprising a data payload and an error correction code generated from the data payload;
wherein the data payload of the first codeword comprises a first logical-to-physical address table entry read from the non-volatile memory and a portion of a second logical-to-physical address table entry read from the non-volatile memory; and
wherein a data payload of the second codeword comprises a remainder of the second logical-to-physical address table entry.

2. A storage system comprising:
a non-volatile memory;
a volatile memory; and
a controller configured to store first and second codewords in the volatile memory, each of the first and second codewords comprising a data payload and an error correction code generated from the data payload;
wherein the data payload of the first codeword comprises a first logical-to-physical address table entry read from the non-volatile memory and a portion of a second logical-to-physical address table entry read from the non-volatile memory; and
wherein a data payload of the second codeword comprises a remainder of the second logical-to-physical address table entry.

3. The storage system of claim 2 , wherein the data payload of each of the first and second codewords comprise 62 bytes, and wherein the error correction code of each of the first and second codewords comprise two bytes.

4. The storage system of claim 2 , wherein each of the first and second codewords are configured to store a non-integer number of logical-to-physical address table entries.

5. The storage system of claim 4 , wherein each of the first and second codewords is configured to store 15 complete logical-to-physical address table entries and half of an additional logical-to-physical address table entry.

6. The storage system of claim 2 , wherein the error correction code comprises a first error correction code in the first codework and a second error correction code in the second codeword, and wherein the second logical-to-physical address table entry is partially protected by the first error correction code in the first codeword and partially protected by the second error correction code in the second codeword.

7. The storage system of claim 2 , further comprising a four-byte-wide bus between the controller and the volatile memory.

8. The storage system of claim 2 , wherein reading the first logical-to-physical address table entry from the volatile memory requires a single minimum read transaction, and wherein reading the second logical-to-physical address table entry from the volatile memory requires two minimum read transactions.

9. The storage system of claim 2 , wherein updating the first logical-to-physical address table entry in the volatile memory requires two minimum write transactions, and wherein updating the second logical-to-physical address table entry in the volatile memory requires four minimum write transactions.

10. The storage system of claim 9 , wherein the four minimum read transactions comprise read-modify-write operations, and wherein updating the second logical-to-physical address table entry in the volatile memory only requires two minimum write transactions in response to read-modify-write caching being used.

11. The storage system of claim 2 , wherein the controller is further configured to vary a number of logical-to-physical address table entries in the data payload of the first codeword.

12. The storage system of claim 11 , wherein the controller is further configured to vary the number of logical-to-physical address table entries by:
determining that the first codeword contains a specified logical-to-physical address table entry;
extracting the specified logical-to-physical address table entry from the data payload of the first codeword to identify a previous address; and
modifying the specified logical-to-physical address table entry with the previous address.

13. The storage system of claim 2 , wherein the non-volatile memory comprises a three-dimensional memory.

14. In a storage system comprising a non-volatile memory and a volatile memory, a method comprising:
storing a codeword in the volatile memory, wherein the codeword comprises a data portion and an error correction code generated from the data portion, wherein the data portion comprises a complete logical-to-physical address table entry read from the non-volatile memory and a partial logical-to-physical address table entry read from the non-volatile memory; and
storing at least one additional codeword in the volatile memory, wherein the at least one additional codeword comprises a remainder of the partial logical-to-physical address table entry.

15. The method of claim 14 , wherein the at least one additional codeword comprises at least one additional error correction code, wherein the data payload of each codeword comprises 62 bytes, and wherein the error correction code of each codeword comprises two bytes.

16. The method of claim 14 , wherein each codeword is configured to store 15 complete logical-to-physical address table entries and half of an additional logical-to-physical address table entry.

17. The method of claim 14 , wherein reading the complete logical-to-physical address table entry from the volatile memory requires a single minimum read transaction, and wherein reading a logical-to-physical address table entry split among codewords requires two minimum read transactions.

18. The method of claim 14 , wherein updating the complete logical-to-physical address table entry in the volatile memory requires two minimum write transactions, and wherein updating a logical-to-physical address table entry split among codewords requires four minimum write transactions without read-modify-write caching or two minimum write transactions with read-modify-write caching.

19. The method of claim 14 , further comprising varying a number of logical-to-physical address table entries in a data payload of a codeword.

20. The method of claim 19 , wherein the number of logical-to-physical address table entries are varied by:
determining that the codeword contains a specified logical-to-physical address table entry;
extracting the specified logical-to-physical address table entry from the data payload of the codeword to identify a previous address; and
modifying the specified logical-to-physical address table entry with the previous address.

Assignees

• Western Digital Tech Inc

Inventors

• Walsh James J
• Gold Stephen
• Meyer David R
• Shivhare Vivek

Classifications

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title

• G06F13/1678 Primary

  using bus width · CPC title

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F12/0292

  using tables or multilevel address translation means (G06F12/023 takes precedence; address translation in virtual memory systems G06F12/10) · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title