Multiple ECC codeword sizes in an SSD

Patent metadata

Field	Value
Publication number	US-9430326-B2
Application number	US-201414338264-A
Country	US
Kind code	B2
Filing date	Jul 22, 2014
Priority date	Jul 22, 2014
Publication date	Aug 30, 2016
Grant date	Aug 30, 2016

Abstract

Methods for writing multiple codewords having multiple sizes to a solid-state device are provided. In one aspect, a method includes receiving a plurality of host data units for storage in a solid-state non-volatile memory. The method includes dividing the plurality of host data units among a plurality of data payloads, wherein a first data payload comprises a first host data unit and a second data payload comprises a portion of a second host data unit. The method includes encoding the first data payload into a first codeword having a first codeword size. The method includes encoding the second data payload into a second codeword having a second codeword size, the second codeword size being different from the first codeword size. The method includes writing the first codeword and the second codeword to a first page in the solid-state non-volatile memory. Systems and machine-readable media are also provided.

First claim

What is claimed is:

1. A method for storing data in a solid-state device, the method comprising:
receiving a plurality of host data units for storage in a solid-state non-volatile memory;
dividing the plurality of host data units among a plurality of data payloads, wherein a first data payload comprises a first host data unit and a second data payload comprises a portion of a second host data unit;
encoding the first data payload into a first error-correcting code (ECC) codeword having a first codeword size;
encoding the second data payload into a second ECC codeword having a second codeword size, the second codeword size being different from the first codeword size; and
writing the first ECC codeword and the second ECC codeword to a first page in the solid-state non-volatile memory,
wherein the first ECC codeword and the second ECC codeword comprise a number of parity bits, and
wherein the number of parity bits in the first ECC codeword is the same as the number of parity bits in the second ECC codeword.

2. The method of claim 1 , further comprising:
encoding a set of data payloads into a plurality of ECC codewords having the first codeword size, wherein the set of data payloads comprises two or more data payloads from the plurality of data payloads; and
writing the plurality of ECC codewords having the first codeword size to the first page in the solid-state non-volatile memory.

3. The method of claim 1 , wherein a third data payload comprises a remaining portion of the second host data unit, and the method further comprises:
dividing a remaining portion of the second host data unit into a third data payload;
encoding the third data payload into a third ECC codeword having a third codeword size, the third codeword size being different from the first codeword size and the second codeword size; and
writing the third ECC codeword to a second page in the solid-state non-volatile memory.

4. The method of claim 3 , wherein the first page and the second page are sequential in order in the solid-state non-volatile memory.

5. The method of claim 3 , wherein the second page comprises three ECC codewords each having a different codeword size.

6. The method of claim 1 , wherein a plurality of ECC codewords are written and arranged in a repeating pattern of codeword sizes across a plurality of pages in the solid-state non-volatile memory.

7. The method of claim 1 , wherein the first codeword size and the second codeword size are selected from a plurality of codeword sizes.

8. The method of claim 1 , wherein each of the plurality of host data units is of a same size, and wherein the first data payload is of a different size from the second data payload.

9. The method of claim 1 , wherein dividing the plurality of host data units among the plurality of data payloads comprises allocating an amount based on a codeword size to be written to the solid-state non-volatile memory.

10. A system, comprising:
a solid-state non-volatile memory;
one or more data buffers configured to receive a plurality of host data units for storage in the solid-state non-volatile memory;
a controller configured to:
divide the plurality of host data units in the one or more data buffers among a plurality of data payloads, wherein a first data payload comprises a first host data unit and a second data payload comprises a portion of a second host data unit; and

an encoder/decoder configured to:
encode the first data payload into a first error-correcting code (ECC) codeword having a first codeword size; and
encode the second data payload into a second ECC codeword having a second codeword size, the second codeword size being different from the first codeword size,

wherein the controller is further configured to write the first ECC codeword and the second ECC codeword to a first page in the solid-state non-volatile memory,
wherein the first ECC codeword and the second ECC codeword comprise a number of parity bits, and
wherein the number of parity bits in the first ECC codeword is the same as the number of parity bits in the second ECC codeword.

11. The system of claim 10 , wherein the encoder/decoder is further configured to encode a set of data payloads into a plurality of ECC codewords having the first codeword size, wherein the set of data payloads comprises two or more data payloads from the plurality of data payloads, and the controller is further configured to write the plurality of ECC codewords having the first codeword size to the first page in the solid-state non-volatile memory.

12. The system of claim 10 , wherein a third data payload comprises a remaining portion of the second host data unit,
wherein the controller is further configured to divide a remaining portion of the second host data unit into a third data payload,
wherein the encoder/decoder is further configured to encode the third data payload into a third ECC codeword having a third codeword size, the third codeword size being different from the first codeword size and the second codeword size, and
wherein the controller is further configured to write the third ECC codeword to a second page in the solid-state non-volatile memory.

13. The system of claim 12 , wherein the first page and the second page are sequential in order in the solid-state non-volatile memory.

14. The system of claim 12 , wherein the second page comprises three ECC codewords each having a different codeword size.

15. The system of claim 10 , wherein a plurality of ECC codewords are written and arranged in a repeating pattern of codeword sizes across a plurality of pages in the solid-state non-volatile memory.

16. The system of claim 10 , wherein the first codeword size and the second codeword size are selected from a plurality of codeword sizes.

17. The system of claim 16 , wherein the plurality of codeword sizes are based on a capability of the encoder/decoder.

18. The system of claim 10 , wherein dividing the plurality of host data units among the plurality of data payloads comprises allocating an amount based on a codeword size to be written to the solid-state non-volatile memory.

19. A non-transitory machine-readable media including instructions thereon that, when executed, perform a method, the method comprising:
receiving a plurality of host data units for storage in a solid-state non-volatile memory;
dividing the plurality of host data units among a plurality of data payloads, wherein a first data payload comprises a first host data unit and a second data payload comprises a portion of a second host data unit;
encoding the first data payload into a first error-correcting code (ECC) codeword having a first codeword size;
encoding the second data payload into a second ECC codeword having a second codeword size, the second codeword size being different from the first codeword size; and
writing the first ECC codeword and the second ECC codeword to a first page in the solid-state non-volatile memory,
wherein the first ECC codeword and the second ECC codeword comprise a number of parity bits, and
wherein the number of parity bits in the first ECC codeword is the same as the number of parity bits in the second ECC codeword.

Assignees

• HGST Netherlands BV

Inventors

• Barndt Richard David

Classifications

• G06F11/1068 Primary

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title