Method of forming a low loss electronics assembly

Patent metadata

Field	Value
Publication number	US-11546995-B2
Application number	US-202117519653-A
Country	US
Kind code	B2
Filing date	Nov 5, 2021
Priority date	Oct 10, 2019
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

A method of forming an electronics assembly includes providing a substrate, attaching an electronics component to the substrate, disposing one or more dielectric ramps on the substrate along at least a portion of a perimeter of the electronics component, disposing a first ground plane over the substrate and the dielectric ramp(s), disposing a first dielectric over the first ground plane, disposing a stripline over the first dielectric, disposing a second dielectric over the stripline and the first dielectric, and disposing a second ground plane over the second dielectric.

First claim

What is claimed is:

1. A method of forming an electronics assembly, the method comprising:
disposing one or more dielectric ramps on a substrate along at least a portion of a perimeter of an electronics component;
disposing a first ground plane over the substrate and the one or more dielectric ramps;
disposing a first dielectric over the first ground plane; and
disposing a stripline over the first dielectric.

2. The method of claim 1 , further comprising disposing a second dielectric over the stripline and the first dielectric.

3. The method of claim 2 , wherein said disposing the second dielectric comprises disposing the second dielectric over the electronics component.

4. The method of claim 2 , further comprising disposing a second ground plane over the second dielectric.

5. The method of claim 4 , further comprising interconnecting the first ground plane and the second ground plane.

6. The method of claim 4 , further comprising interconnecting the electronics component and the second ground plane.

7. The method of claim 4 , wherein said disposing the second dielectric comprises printing the second dielectric, and wherein said disposing the second ground plane comprises printing the second ground plane.

8. The method of claim 1 , wherein said disposing the one or more dielectric ramps comprises printing the one or more dielectric ramps, wherein said disposing the first ground plane comprises printing the first ground plane, wherein said disposing the first dielectric comprises printing the first dielectric, and wherein said disposing the stripline comprises printing the stripline.

9. The method of claim 1 , wherein said disposing the stripline comprises extending the stripline to contact at least one pad of the electronics component.

10. The method of claim 1 , wherein said disposing the first ground plane comprises refraining from disposing the first ground plane over the electronics component.

11. An electronics assembly, comprising:
an electronics component coupled to a substrate;
one or more dielectric ramps disposed on the substrate;
a first ground plane disposed over the substrate and the one or more dielectric ramps;
a first dielectric disposed over the first ground plane; and
a stripline disposed over the first dielectric.

12. The electronics assembly of claim 11 , further comprising a second dielectric disposed over the stripline and the first dielectric.

13. The electronics assembly of claim 12 , wherein the second dielectric is disposed over the electronics component.

14. The electronics assembly of claim 12 , further comprising a second ground plane disposed over the second dielectric.

15. The electronics assembly of claim 14 , wherein the first ground plane and the second ground plane are interconnected.

16. The electronics assembly of claim 14 , wherein the electronics component and the second ground plane are interconnected.

17. The electronics assembly of claim 11 , wherein the stripline contacts at least one pad of the electronics component.

18. The electronics assembly of claim 16 , further comprising interconnects that interconnect a ground paddle of the electronics component and a second ground plane.

19. The electronics assembly of claim 11 , further comprising:
first interconnects that interconnect the first ground plane and a second ground plane; and
second interconnects that interconnect a ground paddle of the electronics component and the second ground plane.

20. The electronics assembly of claim 11 , wherein the first ground plane comprises does not extend over the electronics component.

Assignees

• Boeing Co

Inventors

• Rogers John E

Classifications

• H05K1/148

  Arrangements of two or more hingeably connected rigid printed circuit boards, i.e. connected by flexible means · CPC title

• B29C64/141

  using only solid materials · CPC title

• H05K2201/09618

  Via fence, i.e. one-dimensional array of vias · CPC title

• H05K1/185 Primary

  associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards · CPC title

• H05K2201/0723

  provided by an inner layer of PCB · CPC title