Analog-to-digital converter with auto-zeroing residue amplification circuit

Patent metadata

Field	Value
Publication number	US-11545991-B2
Application number	US-202117524542-A
Country	US
Kind code	B2
Filing date	Nov 11, 2021
Priority date	Aug 11, 2020
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

Disclosed herein are some examples of analog-to-digital converters (ADCs) that can perform auto-zeroing with amplifying a signal for improvement of a signal-to-noise ratio. The ADCs may produce a first digital code to represent an analog input signal and a second digital code based on a residue from the first digital code, and may combine the first digital code and the second digital code to produce a digital output code to represent the analog input signal. The ADC may utilize a first observation and a second observation of an analog residue value representing the residue to produce the second digital code.

First claim

What is claimed is:

1. A circuit, comprising:
an analog-to-digital converter (ADC) to receive an analog input value;
a digital-to-analog converter (DAC) coupled to an output of the ADC;
subtractor circuitry to produce a positive component of a residue value and a negative component of the residue value at a positive terminal and a negative terminal respectively, the residue value being a difference between the analog input value and the output of the DAC;
a first switch and a second switch coupled to the positive terminal and the negative terminal respectively, the first switch and the second switch being open during a first phase and closed during a second phase;
a third switch and a fourth switch coupled to the negative terminal and the positive terminal respectively, the third switch and the fourth switch are closed during the first phase and open during the second phase; and
an active circuit having a positive terminal coupled to the first switch and the third switch and a negative terminal coupled to the second switch and the fourth switch.

2. The circuit of claim 1 , further comprising:
a further ADC coupled to an output of the active circuit.

3. The circuit of claim 2 , wherein the further ADC is to make a first observation of the output of the active circuit during the first phase, and make a second observation of the output of the active circuit during the second phase.

4. The circuit of claim 2 , further comprising:
a digital circuit to receive a first digital code based on a first observation of the output of the active circuit made during the first phase and to receive a second digital code based on a second observation of the output of the active circuit made during the second phase.

5. The circuit of claim 4 , wherein the digital circuit is to receive a further digital code from the further ADC.

6. The circuit of claim 4 , wherein the digital circuit is to output a final digital code representative of the analog input value.

7. The circuit of claim 2 , wherein the further ADC comprises a first quantizer and a second quantizer, the first quantizer is to make a first observation of the output of the active circuit during the first phase, and the second quantizer is to make a second observation of the output of the active circuit during the second phase.

8. A circuit, comprising:
a positive terminal to receive a positive component of a residue value, the residue value being a difference between an analog input value and a digital code generated from the analog input value;
a negative terminal to receive a negative component of the residue value;
a first switch and a second switch coupled to the positive terminal and the negative terminal respectively, the first switch and the second switch being open during a first phase and closed during a second phase;
a third switch and a fourth switch coupled to the negative terminal and the positive terminal respectively, the third switch and the fourth switch are closed during the first phase and open during the second phase; and
an active circuit having a positive input terminal coupled to the first switch and the third switch and a negative input terminal coupled to the second switch and the fourth switch.

9. The circuit of claim 8 , further comprising:
a first capacitor couplable to a positive output terminal of the active circuit during the first phase;
a second capacitor couplable to a negative output terminal of the active circuit during the first phase;
a third capacitor couplable to the negative output terminal of the active circuit during the second phase; and
a fourth capacitor couplable to the positive output terminal of the active circuit during the second phase.

10. The circuit of claim 9 , further comprising:
first switch to couple the first capacitor to a positive input node of a comparing circuit during a fourth phase;
comparing switch to couple the second capacitor to a negative input node of the comparator circuit during the fourth phase;
third switch to couple the third capacitor to the positive input node of the comparing circuit during the fourth phase; and
fourth switch to couple the fourth capacitor to the negative input node of the comparing circuit during the fourth phase.

11. The circuit of claim 10 , further comprising:
a first capacitive digital-to-analog converter segment coupled to the positive input node of the comparing circuit; and
a second capacitive digital-to-analog converter segment coupled to the negative input node of the comparing circuit.

12. The circuit of claim 10 , further comprising:
a digital state machine coupled to an output of the comparing circuit.

13. The circuit of claim 8 , further comprising:
a first capacitive digital-to-analog converter segment couplable to an output of the active circuit during the first phase; and
a second capacitive digital-to-analog converter segment couplable to the output of the active circuit during the second phase, but in opposite polarity relative to the first phase.

14. The circuit of claim 8 , further comprising:
a third capacitive digital-to-analog converter segment couplable to sample a dither value.

15. The circuit of claim 9 , switches to short one side of the first capacitor, the second capacitor, and the third capacitor, and the fourth capacitor together.

16. The circuit of claim 8 , further comprising:
a first capacitive digital-to-analog converter segment couplable to sample a first analog value;
a second capacitive digital-to-analog converter segment couplable to sample a second analog value; and
a third capacitive digital-to-analog converter segment couplable to sample a third analog value.

17. A circuit, comprising:
a positive input terminal to receive a positive component of a residue value, the residue value being a difference between an analog input value and a digital code generated from the analog input value;
a negative input terminal to receive a negative component of the residue value;
a first switch and a second switch coupled to the positive terminal and the negative terminal respectively, operable to conduct the residue value having a first polarity during a first phase;
a third switch and a fourth switch coupled to the negative terminal and the positive terminal respectively, operable to conduct the residue value having a second polarity during a second phase, the second polarity being opposite of the first polarity;
a transconductance circuit coupled to receive the residue value during the first phase and the second phase;
first and second capacitors to integrate the residue value having the first polarity during the first phase;
third and fourth capacitors to integrate the residue value having the second polarity during the second phase;
switches operable to short one plate of the first and third capacitors together at a positive output terminal during a third phase; and
switches operable to short one plate of the second and fourth capacitors together at a negative output terminal during the third phase.

18. The circuit of claim 17 , further comprising:
a residue generating circuit to output the positive component and the negative component of the residue value at the positive input terminal and the negative input terminal respectively.

19. The circuit of claim 17 , further comprising:
an analog-to-digital converter coupled to the positive output terminal and the negative output terminal.

20. The circuit of claim 17 , further comprising:
a comparing circuit coupled to the positive output term

Assignees

• Analog Devices Inc

Inventors

• Steensgaard-Madsen Jesper
• Thomas Andrew J

Classifications

• H03M1/466

  using switched capacitors · CPC title

• H03F3/38

  DC amplifiers with modulator at input and demodulator at output; Modulators or demodulators specially adapted for use in such amplifiers {(switched capacitor amplifiers H03F3/005)} · CPC title

• H03M1/44

  Sequential comparisons in series-connected stages with change in value of analogue signal · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03M1/442

  using switched capacitors · CPC title