Method and apparatus for controlling clock cycle time

Patent metadata

Field	Value
Publication number	US-11545988-B2
Application number	US-202217679999-A
Country	US
Kind code	B2
Filing date	Feb 24, 2022
Priority date	Feb 11, 2020
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

A circuit and corresponding method control cycle time of an output clock used to clock at least one other circuit. The circuit comprises an agile ring oscillator (ARO) and ARO controller. The ARO includes at least one instance of a first ring oscillator (RO) and second RO that generate high and low phases, respectively, of cycles of the output clock. The ARO controller controls durations of the high and low phases, independently, via first and second control words output to the ARO, respectively. In a present cycle of the output clock, the ARO controller effects a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected usage of the at least one other circuit in the next cycle. The change improves a performance-to-power ratio of the at least one other circuit.

First claim

What is claimed is:

1. A circuit comprising:
at least one instance of a first ring oscillator (RO) and a second RO, the first and second ring oscillators configured to generate high and low phases, respectively, of cycles of an output clock; and
a controller configured to control durations of the high and low phases.

2. The circuit of claim 1 , wherein:
the controller is further configured to control durations of the high and low phases, independently, via first and second control words, respectively.

3. The circuit of claim 1 , wherein:
the controller is further configured to (i) control durations of the high and low phases, independently, via first and second control words output, respectively, and (ii) in a present cycle of the output clock, effect a change to the high or low phase, or a combination thereof, in a next cycle of the output clock by updating the first or second control word, or a combination thereof, based on an indication of expected activity or inactivity of at least one other circuit expected in the next cycle.

4. The circuit of claim 3 , wherein the circuit further includes an instruction decoder and wherein the instruction decoder is configured to identify instructions to be executed by at least one other circuit and wherein the indication represents whether the at least one other circuit will be executing at least one instruction in the next cycle.

5. The circuit of claim 1 , wherein:
the controller is further configured to (i) control durations of the high and low phases, independently and (ii) in a present cycle of the output clock, effect a change to the high or low phase, or a combination thereof, in a next cycle of the output clock based on an indication of expected usage of at least one other circuit in the next cycle; and
the output clock is associated with a target frequency, wherein, in an event the indication indicates that the at least one other circuit is expected to be active in the next cycle, the change causes a frequency of the output clock to be lower or higher than the target frequency by altering a period of the output clock in the next cycle by changing a respective target count of signal inversions of a respective signal propagated in the first RO, second RO, or a combination thereof.

6. The circuit of claim 1 , wherein the controller is further configured to:
control durations of the high and low phases, independently, via first and second control words, respectively;
maintain first and second calibration control words for updating the first and second control words, respectively, to cause the output clock to be generated with a target frequency; and
maintain first and second slower control words for configuring the first and second control words, respectively, to cause the output clock to be generated with a slower frequency that is slower relative to the target frequency.

7. The circuit of claim 6 , wherein the controller is further configured to relax timing, in a next cycle, by updating, in a present cycle, the first and second control words to be the first and second slower control words, respectively, causing a cycle time of the output clock to increase in the next cycle.

8. The circuit of claim 6 , wherein, in an event an indication of expected usage of at least one other circuit in a next cycle changes state in a present cycle and the first and second control words are configured, in the present cycle, as the first and second calibration control words, respectively, the controller is further configured to update the first and second control words to be the first and second slower control words, respectively.

9. The circuit of claim 6 , wherein, in an event an indication of expected usage of at least one other circuit in a next cycle changes state in a present cycle and the first and second control words are, presently, configured to be the first and second slower control words, respectively, the controller is further configured to update the first and second control words, in the present cycle, to the first and second calibration control words, respectively.

10. The circuit of claim 6 , wherein, the controller is further configured to:
adjust the first and second calibration control words based on a calibration cycle; and
update the first and second control words to the first and second calibration control words, respectively, in response to such adjustment and based on an indication of expected usage of at least one other circuit.

11. The circuit of claim 10 , wherein:
the controller includes a calibration counter;
the controller is further configured to reset and reload the calibration counter with a target reference count at a start of the calibration cycle;
the target reference count is based on the target frequency and a time window between the start of the calibration cycle and an end of the calibration cycle;
the calibration counter is configured to be triggered by the output clock; and
the first and second calibration control words are adjusted based on a value of the calibration counter at the end of the calibration cycle.

12. The circuit of claim 6 , wherein the slower frequency represents a slowest frequency for a voltage below which at least one other circuit is unable to perform its intended function at the voltage.

13. The circuit of claim 1 , wherein:
the first RO is used to reset and enable the second RO;
the second RO is used to reset and enable the first RO;
the first RO includes a first plurality of inverting gates formed in a first ring;
the first RO is coupled to a first multiplexer;
the first multiplexer is coupled to a first counter configured to generate a first done signal;
the first RO, first multiplexer, and first counter, in combination, are configured to count a first target number of inversions propagated along the first plurality of inverting gates, the first multiplexer configured to select a given first inverting gate of the plurality of first inverting gates based on a first control word, the given first inverting gate selected to trigger the first counter;
the second RO includes a second plurality of inverting gates formed in a second ring;
the second RO is coupled to a second multiplexer;
the second multiplexer is coupled to a second counter configured to generate a second done signal;
the second RO, second multiplexer, and second counter are configured, in combination, to count a second target number of inversions propagated along the second plurality of inverting gates, the second multiplexer configured to select a given second inverting gate of the plurality of second inverting gates based on a second control word, the second inverting gate selected to trigger the second counter.

14. The circuit of claim 13 , wherein the circuit is configured to:
employ the first done signal to reset the second RO and cause the second counter to be reset and re-loaded with the second target number; and
employ the second done signal to reset the first RO and cause the first counter to be reset and re-loaded with the first target number, the first and second target numbers configured based on a target frequency for at least one other circuit.

15. The circuit of claim 13 , further comprising a clock output circuit configured to output the output clock based on the first and second done signals.

16. The circuit of claim 1 , wherein the output clock is used to clock at least one other circuit and wherein the at least one other circuit has a single clock domain.

17. The circuit of claim 1 , wherein the at least one instance includes a first instance and a second instance an

Assignees

• Marvell Asia Pte Ltd

Inventors

• Rosen Eitan
• Norman Oded

Classifications

• H03K5/13

  Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals · CPC title

• H03K3/0315 Primary

  Ring oscillators · CPC title

• H03L7/16 Primary

  Indirect frequency synthesis, i.e. generating a desired one of a number of predetermined frequencies using a frequency- or phase-locked loop · CPC title

• H03L7/0996

  Selecting a signal among the plurality of phase-shifted signals produced by the ring oscillator · CPC title

• H03L7/0995

  the oscillator comprising a ring oscillator · CPC title