Method and apparatus for synchronization

Patent metadata

Field	Value
Publication number	US-9973331-B1
Application number	US-201715429609-A
Country	US
Kind code	B1
Filing date	Feb 10, 2017
Priority date	Feb 25, 2009
Publication date	May 15, 2018
Grant date	May 15, 2018

Abstract

Aspects of the disclosure provide a circuit that includes a clock synchronization circuit. The clock synchronization circuit is configured to determine a sub-cycle offset between a first clock signal and a second clock signal, and select rising/failing edges of the first clock signal and the second clock signal based on the sub-cycle offset for enabling communication between a first clock domain that is operative in response to the first clock signal and a second clock domain that is operative in response to the second clock signal.

First claim

What is claimed is:

1. A processor system including two or more communicatively coupled globally asynchronous processors, the processor system comprising:
a sampling clock edge determination circuit associated with a first processor, the sampling clock edge determination circuit configured to determine a clock edge of an interface clock signal for subsequently sampling a second processor signal, the determined clock edge being independent of a previously determined clock edge, the second processor signal being received from a second processor that is operated asynchronously with respect to the first processor.

2. The processor system of claim 1 , further comprising:
a transmitting circuit configured to transmit a first processor signal from the first processor to the second processor in response to edges of the interface clock signal; and
a sampling circuit configured to sample the second processor signal transmitted from the second processor to the first processor in response to the edges of the interface clock signal.

3. The processor system of claim 1 , further comprising:
a clock synchronization circuit configured to determine a sub-cycle offset between a first clock signal of the first processor and a second clock signal of the second processor, and determine clock edges of the interface clock signal by selecting rising/failing edges of the first clock signal and the second clock signal based on the sub-cycle offset.

4. The processor system of claim 1 , further comprising:
a sub-cycle offset determination circuit configured to determine an offset in a cycle between a first clock signal of the first processor and a second clock signal of the second processor, wherein the sampling clock edge determination circuit selects a current clock edge determined in a current clock cycle based on the offset.

5. The processor system of claim 4 , wherein when the offset in the cycle between the first clock signal of the first processor and the second clock signal of the second processor is outside of a clock cycle range of the first clock signal, then the sampling clock edge determination circuit skips a clock cycle and selects the clock edge of the interface clock signal from a next clock cycle.

6. The processor system of claim 4 , wherein the sub-cycle offset determination circuit determines the offset in the cycle between the first clock signal and the second clock signal as a number of delay units.

7. The processor system of claim 6 , wherein the sub-cycle offset determination circuit is configured to determine a first number of delay units corresponding to the first clock cycle of the first clock signal, a second number of delay units corresponding to the second clock cycle of the second clock signal, and a third number of delay units corresponding to the offset in the cycle between the first clock signal and the second clock signal.

8. The processor system of claim 1 , wherein the sampling clock edge determination circuit associated with the first processor is further configured to determine a second clock edge of a second interface clock signal for subsequently sampling a first processor signal, the determined second clock edge being independent of a previously determined second clock edge, the first processor signal being from the first processor that is operated asynchronously with respect to the second processor.

9. The processor system of claim 8 , further comprising:
a first transmitting circuit configured to transmit a first transmitted signal from the first processor to the second processor in response to edges of the interface clock; and
a first sampling circuit configured to sample a first signal transmitted from the second processor to the first processor in response to the edges of the interface clock;
a second transmitting circuit configured to transmit a second transmitted signal from the second processor to the first processor in response to edges of the second interface clock; and
a second sampling circuit configured to sample a second signal transmitted from the first processor to the second processor in response to the edges of the second interface clock.

Assignees

• Marvell Israel Misl Ltd
• Marvell Israel M L S L Ltd

Inventors

• Rosen Eitan

Classifications

• H03K3/0315

  Ring oscillators · CPC title

• H04L7/0037

  Delay of clock signal · CPC title

• H04L7/0087 Primary

  Preprocessing of received signal for synchronisation, e.g. by code conversion, pulse generation or edge detection · CPC title

• H04L7/0091

  Transmitter details · CPC title

• H03L7/00 Primary

  Automatic control of frequency or phase; Synchronisation · CPC title