Manufacturing method of semiconductor device

Patent metadata

Field	Value
Publication number	US-11545502-B2
Application number	US-202017032839-A
Country	US
Kind code	B2
Filing date	Sep 25, 2020
Priority date	Oct 17, 2019
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

A manufacturing method of a semiconductor device includes: (a) forming a gate structure for a control gate electrode on a semiconductor substrate; (b) forming a charge storage film so as to cover a first side surface, a second side surface, and an upper surface of the gate structure; (c) forming a conductive film for a memory gate electrode on the charge storage film; (d) removing a part of the charge storage film and a part of the conductive film such that the charge storage film and the conductive film remain in this order on the first side surface and the second side surface of the gate structure, thereby forming the memory gate electrode; and (e) removing apart of the gate structure separate from the first side surface and the second side surface such that a part of the semiconductor substrate is exposed from the gate structure.

First claim

What is claimed is:

1. A manufacturing method of a semiconductor device, the manufacturing method comprising:
(a) forming a gate structure for a control gate electrode on a semiconductor substrate via a gate insulating film;
(b) forming a charge storage film on the semiconductor substrate so as to cover a first side surface, a second side surface, and an upper surface of the gate structure;
(c) forming a first conductive film for a memory gate electrode on the charge storage film;
(d) removing a part of the charge storage film and a part of the first conductive film such that the charge storage film and the first conductive film remain in this order on the first side surface and the second side surface of the gate structure on the semiconductor substrate, thereby forming the memory gate electrode; and
(e) removing a part of the gate structure separate from the first side surface and the second side surface such that a part of the semiconductor substrate is exposed from the gate structure,
wherein the (a) includes:
(a1) forming a stacked film in which a second conductive film for a control gate electrode and a cap insulating film are stacked in this order, on the gate insulating film;
(a2) forming a first gate structure portion and a second gate structure portion separate from each other by removing a part of the stacked film; and
(a3) forming a sacrificial layer on the semiconductor substrate so as to fill an opening formed between the first gate structure portion and the second gate structure portion, and

wherein the sacrificial layer is removed in the (e).

2. The manufacturing method of the semiconductor device according to claim 1 , wherein the (a3) includes:
(a3-1) forming a first layer on an inner surface of the opening; and
(a3-2) forming a second layer on the first layer so as to fill the opening.

3. The manufacturing method of the semiconductor device according to claim 1 , wherein the gate structure includes:
the first gate structure portion having the first side surface and a third side surface located on an opposite side to the first side surface;
the second gate structure portion having the second side surface and a fourth side surface located on an opposite side to the second side surface; and
the sacrificial layer formed between the third side surface and the fourth side surface.

4. The manufacturing method of the semiconductor device according to claim 1 , wherein the (a3) includes:
(a3-1) forming the sacrificial layer on the semiconductor substrate so as to cover the first gate structure portion and the second gate structure portion; and
(a3-2) patterning the sacrificial layer such that a part of the sacrificial layer formed in the opening formed between the first gate structure portion and the second gate structure portion remains.

5. The manufacturing method of the semiconductor device according to claim 4 , wherein the (a3-2) includes:
polishing a part of the sacrificial layer located above a first upper surface of the first gate structure portion and a part of the sacrificial layer located above a second upper surface of the second gate structure portion; and
removing a part of the sacrificial layer located outside the opening.

6. The manufacturing method of the semiconductor device according to claim 1 , wherein a material of the sacrificial layer is polycrystalline silicon.

7. The manufacturing method of the semiconductor device according to claim 1 , wherein a part of the gate structure is removed by anisotropic etching in the (e).

8. The manufacturing method of the semiconductor device according to claim 1 ,
wherein, in the (b), a stacked film in which a first insulating film, a high dielectric constant film, and a second insulating film are formed in this order is formed as the charge storage film, and
wherein the high dielectric constant film contains a material whose dielectric constant is higher than that of silicon nitride.

9. The manufacturing method of the semiconductor device according to claim 8 , wherein the material in the high dielectric constant film is hafnium.

10. The manufacturing method of the semiconductor device according to claim 8 , wherein the second insulating film contains a material whose dielectric constant is higher than that of silicon nitride.

11. The manufacturing method of the semiconductor device according to claim 1 , further comprising, after the (e),
(f) forming an impurity region in the semiconductor substrate by an ion implantation method using the control gate electrode as an implantation mask.

12. A manufacturing method of a semiconductor device, the manufacturing method comprising:
(a) forming a gate structure for a control gate electrode on a semiconductor substrate via a gate insulating film;
(b) forming a charge storage film on the semiconductor substrate so as to cover a first side surface, a second side surface, and an upper surface of the gate structure;
(c) forming a first conductive film for a memory gate electrode on the charge storage film;
(d) removing a part of the charge storage film and a part of the first conductive film such that the charge storage film and the first conductive film remain in this order on the first side surface and the second side surface of the gate structure on the semiconductor substrate, thereby forming the memory gate electrode; and
(e) removing a part of the gate structure separate from the first side surface and the second side surface such that a part of the semiconductor substrate is exposed from the gate structure,
wherein the (a) includes:
(a1) forming a stacked film in which a second conductive film for a control gate electrode and a cap insulating film are stacked in this order, on the gate insulating film; and
(a2) removing a part of the stacked film to form the gate structure configured of the other part of the stacked film.

Assignees

• Renesas Electronics Corp

Inventors

• Maruyama Takuya
• Maruyama Takahiro

Classifications

• H01L29/42344

  Electricity · mapped topic

• H01L29/40117

  Electricity · mapped topic

• H01L27/11568 Primary

  Electricity · mapped topic

• H01L29/66833

  Electricity · mapped topic

• H10D64/037

  comprising charge-trapping insulators · CPC title