Semiconductor structure and method for forming the same

Patent metadata

Field	Value
Publication number	US-11545396-B2
Application number	US-202016938269-A
Country	US
Kind code	B2
Filing date	Jul 24, 2020
Priority date	Jul 25, 2019
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

A method for forming a semiconductor structure includes providing a substrate, including a first region and a second region; forming a plurality of fin structures on the substrate; forming an isolation structure between adjacent fin structures; forming a mask layer over the substrate and the plurality of fin structures; forming an opening by removing a portion of the mask layer formed in the first region; removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask; removing the remaining portion of the mask layer; and forming a gate structure across the plurality of fin structures. The gate structure covers the first region.

First claim

What is claimed is:

1. A method for forming a semiconductor structure, comprising:
providing a substrate, including a first region and a second region;
forming a plurality of fin structures on the substrate;
forming an isolation structure between adjacent fin structures;
forming a mask layer over the substrate and the plurality of fin structures;
forming an opening by removing a portion of the mask layer formed in the first region;
removing a portion of the isolation structure exposed in the opening by using a remaining portion of the mask layer as a mask;
removing the remaining portion of the mask layer;
forming a gate structure across the plurality of fin structures, wherein the gate structure covers the first region,
after forming the isolation structure on the substrate:
implanting first conductive ions into each fin structure and the substrate under the fin structure to form a drift region; and
implanting second conductive ions into each fin structure and the substrate under the fin structure on one side of the drift region to form a first doped region; and

after forming the gate structure:
implanting the second conductive ions to each fin structure on a side of the gate structure, where the drift region is formed, to form a second doped region, wherein the second doped region is located on top of the drift region; and
forming a source region and a drain region in each fin structure and respectively on two sides of the gate structure, wherein along a length direction of the fin structure, the second doped region is located between the gate structure and the drain region.

2. The method according to claim 1 , wherein:
a type of the first conductive ions is electrically opposite to a type of the second conductive ions.

3. The method according to claim 2 , wherein:
the first conductive ions are N-type ions, and the second conductive ions are P-type ions.

4. The method according to claim 1 , wherein forming the gate structure includes:
forming a gate oxide layer on top and sidewall surfaces of the plurality of fin structures;
forming a gate material layer on the gate oxide layer; and
performing a CMP process on the gate material layer to form the gate structure.

5. The method according to claim 1 , wherein forming the isolation structure includes:
forming an isolation layer between adjacent fin structures, wherein a top surface of the isolation layer is higher than top surfaces of the plurality of fin structures;
performing a chemical mechanical polishing (CMP) process on the isolation layer until the surface top of the isolation layer is leveled with the top surfaces of the plurality of fin structures; and
etching the isolation layer to form the isolation structure, wherein a top surface of the isolation structure is lower than the top surfaces of the plurality of fin structures.

6. The method according to claim 1 , wherein:
the mask layer is made of a material including a silicon nitride layer or a photoresist layer.

7. The method according to claim 6 , wherein:
forming the mask layer includes a chemical vapor deposition (CVD) process.

8. The method according to claim 1 , wherein forming the opening by removing the portion of the mask layer formed in the first region includes:
forming a photoresist layer on the mask layer;
forming a patterned photoresist layer from the photoresist layer by a photolithography process;
removing a portion of the mask layer formed in the first region by an etching process using the patterned photoresist layer as an etch mask; and
removing the patterned photoresist layer.

9. The method according to claim 8 , wherein:
removing the portion of the mask layer formed in the first region includes a dry etching process.

10. The method according to claim 1 , wherein:
removing the portion of the isolation structure exposed in the opening includes a dry etching process.

11. The method according to claim 10 , wherein:
an etching gas used in the dry etching process includes carbon tetrafluoride (CF 4 ), octafluorocyclobutane (C 4 F 8 ), trifluoromethane (CHF 3 ), or a combination thereof.

Assignees

• Semiconductor Mfg Int Shanghai Corp
• Semiconductor Mfg Int Beijing Corp

Inventors

• Chen Deyan
• Li Mao
• Jung Dae-Sub

Classifications

• H01L21/823431 Primary

  Electricity · mapped topic

• H01L29/0653

  Electricity · mapped topic

• H01L29/66674

  Electricity · mapped topic

• H01L27/0886

  Electricity · mapped topic

• H01L21/823481

  Electricity · mapped topic