Semiconductor device and manufacturing method of the same

Patent metadata

Field	Value
Publication number	US-11545360-B2
Application number	US-202017033695-A
Country	US
Kind code	B2
Filing date	Sep 26, 2020
Priority date	Jan 22, 2020
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

A manufacturing method of a semiconductor device includes forming a hard mask layer and a photoresist on a substrate having a layer to be etched, and performing exposure and development such that the patterned photoresist has first trenches and to expose the hard mask layer, wherein ends of the first trenches have a width gradually decreased toward an end point. The exposed hard mask layer is removed using the patterned photoresist to transfer the pattern of the first trenches to the hard mask layer such that the patterned hard mask layer has second trenches, and the ends of the second trenches have a width gradually decreased toward an end point. Spacers are formed on inner walls of the second trenches. The hard mask layer is removed such that the layer to be etched is exposed. The exposed layer to be etched is removed using the spacers as an etch mask.

First claim

What is claimed is:

1. A manufacturing method of a semiconductor device, comprising:
forming a layer to be etched on a substrate;
forming at least one hard mask layer on the layer to be etched;
forming a photoresist on the at least one hard mask layer;
performing exposure and development using a photomask such that the patterned photoresist has a plurality of first trenches and to expose the at least one hard mask layer, and an end of each of the first trenches has a width gradually decreased toward an end point, wherein the photomask comprises a plurality of first main patterns arranged in parallel with each other, a second main pattern connected to an end of the plurality of first main patterns, and a plurality of auxiliary patterns spaced a distance from the end of each of the first main patterns to increase a width of the first main patterns at the distance, and the distance is 1.5 times to 2.5 times a first width of each of the first main patterns;
removing the exposed at least one hard mask layer using the patterned photoresist as an etch mask such that a pattern of the plurality of first trenches is transferred to the at least one hard mask layer such that the patterned at least one hard mask layer has a plurality of second trenches, and an end of each of the second trenches has a width gradually decreased toward an end point;
forming spacers on inner walls of the plurality of second trenches;
removing the patterned at least one hard mask layer and exposing the layer to be etched; and
removing the exposed layer to be etched using the spacers as an etch mask.

2. The manufacturing method of the semiconductor device of claim 1 , wherein a third width of the auxiliary patterns is 1.4 times to 1.6 times the first width of each of the first main patterns.

3. The manufacturing method of the semiconductor device of claim 2 , wherein the photoresist is a positive photoresist.

4. The manufacturing method of the semiconductor device of claim 1 , wherein the at least one hard mask layer is formed by stacking different material layers.

5. The manufacturing method of the semiconductor device of claim 1 , wherein the at least one hard mask layer is a single material layer.

6. The manufacturing method of the semiconductor device of claim 1 , wherein a step of forming the at least one hard mask layer on the layer to be etched comprises sequentially forming a carbon layer, a silicon oxynitride layer, and an anti-reflection layer on the layer to be etched.

7. The manufacturing method of the semiconductor device of claim 1 , wherein before a step of Ruining the at least one hard mask layer on the layer to be etched, further comprises forming an intermediate layer on the layer to be etched as an etch stop layer.

8. The manufacturing method of the semiconductor device of claim 1 , wherein the spacers comprise a plurality of lines and a tip portion located at an end of every two of the plurality of lines, wherein the tip portion has a width gradually decreased toward an end point.

9. The manufacturing method of the semiconductor device of claim 8 , wherein a height of the tip portion is substantially equal to a height of each of the plurality of lines.

Assignees

• Winbond Electronics Corp

Inventors

• Lin Tsung-Wei
• Wu Kun-Che
• Wu Chun-Sheng

Classifications

• H10P76/2041 Primary

  Photolithographic processes · CPC title

• H01L21/0274 Primary

  Electricity · mapped topic

• H10P50/695 Primary

  characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask · CPC title