Power manager circuit and electronic device for detecting internal errors

Patent metadata

Field	Value
Publication number	US-11543841-B2
Application number	US-202017069500-A
Country	US
Kind code	B2
Filing date	Oct 13, 2020
Priority date	Mar 19, 2020
Publication date	Jan 3, 2023
Grant date	Jan 3, 2023

Abstract

A power manager circuit is provided. The power manager circuit includes a bandgap reference circuit, first and second monitoring circuits, and a reference buffer. The bandgap reference circuit generates a first voltage, based on an external voltage that is external to the power manager circuit. The first monitoring circuit determines a logical value of a first alarm signal, based on whether a first voltage level of the first voltage is within a first range. The reference buffer generates a second voltage, based on the first voltage. The second monitoring circuit determines a logical value of a second alarm signal, based on whether a second voltage level of the second voltage is within a second range.

First claim

What is claimed is:

1. A power manager circuit comprising:
a bandgap reference circuit configured to generate a first voltage, based on an external voltage that is external to the power manager circuit;
a first monitoring circuit configured to determine a logical value of a first alarm signal, based on whether a first voltage level of the first voltage is within a first range;
a reference buffer configured to generate a second voltage, based on the first voltage; and
a second monitoring circuit configured to determine a logical value of a second alarm signal, based on whether a second voltage level of the second voltage is within a second range.

2. The power manager circuit of claim 1 , wherein the first range is from a first reference level to a second reference level, and
wherein the first monitoring circuit determines the logical value of the first alarm signal, based on a first comparison result of comparing the first reference level and the first voltage level and a second comparison result of comparing the second reference level and the first voltage level.

3. The power manager circuit of claim 2 , wherein the first monitoring circuit generates a first reference voltage having the first reference level and a second reference voltage having the second reference level, by using the external voltage.

4. The power manager circuit of claim 2 , wherein the first monitoring circuit includes:
a first resistor between a power node to which the external voltage is applied and a first node;
a second resistor between the first node and a second node;
a third resistor between the second node and a ground node;
a first comparator comprising a positive terminal connected to the first node and to which a first reference voltage having the first reference level is applied from the first node, and a negative terminal to which the first voltage is applied;
a second comparator comprising a positive terminal to which the first voltage is applied, and a negative terminal connected to the second node and to which a second reference voltage having the second reference level is applied from the second node;
an inverter configured to invert a signal output from the first comparator; and
a NAND gate configured to receive a signal output from the inverter and a signal output from the second comparator, and to output the first alarm signal.

5. The power manager circuit of claim 2 , wherein the first monitoring circuit includes:
a first resistor between a power node to which the external voltage is applied and a first node;
a second resistor between the first node and a second node;
a third resistor between the second node and a ground node;
a first comparator comprising a positive terminal to which the first voltage is applied, and a negative terminal connected to the first node and to which a first reference voltage having the first reference level is applied from the first node;
a second comparator comprising a positive terminal connected to the second node and to which a second reference voltage having the second reference level is applied from the second node, and a negative terminal to which the first voltage is applied;
an inverter configured to invert a signal output from the second comparator; and
a NAND gate configured to receive a signal output from the inverter and a signal output from the first comparator, and to output the first alarm signal.

6. The power manager circuit of claim 2 , wherein the first monitoring circuit includes:
a first resistor between a power node to which the external voltage is applied and a first node;
a second resistor between the first node and a second node;
a third resistor between the second node and a ground node;
a first comparator comprising a positive terminal connected to the first node and to which a first reference voltage having the first reference level is applied from the first node, and a negative terminal to which the first voltage is applied;
a second comparator comprising a positive terminal connected to the second node and to which a second reference voltage having the second reference level is applied from the second node, and a negative terminal to which the first voltage is applied; and
an AND gate configured to receive a signal output from the first comparator and a signal output from the second comparator, and to output the first alarm signal.

7. The power manager circuit of claim 1 , further comprising:
a low drop-out (LDO) regulator configured to generate a third voltage, based on the second voltage; and
a situation monitoring circuit configured to determine whether an error occurs in the power manager circuit, based on the second voltage and the third voltage.

8. The power manager circuit of claim 7 , wherein the situation monitoring circuit includes:
a power detector configured to detect whether an electronic device that includes the power manager circuit is turned on, based on the third voltage;
a glitch detector configured to detect a glitch of the third voltage;
a quiescent current detector configured to measure an amount of power consumption of the LDO regulator;
a start-up detector configured to measure a time length from a time at which the electronic device is turned on to a time at which the third voltage reaches a target voltage level, based on the second voltage and the third voltage;
an oscillation detector configured to detect an oscillation of the third voltage; and
a level detector configured to determine whether the third voltage is within a third range,
wherein the situation monitoring circuit determines whether the error occurs in the power manager circuit, based on information obtained through one or more of the power detector, the glitch detector, the quiescent current detector, the start-up detector, the oscillation detector, and the level detector.

9. An electronic device comprising:
a bandgap reference circuit configured to generate a first voltage, based on an external voltage;
a first monitoring circuit configured to determine whether a first error occurs in the bandgap reference circuit based on the first voltage and to determine a logical value of a first alarm signal depending on whether the first error occurs;
a reference buffer configured to generate a second voltage, based on the first voltage; and
a second monitoring circuit configured to determine whether a second error occurs in the reference buffer based on the second voltage and to determine a logical value of a second alarm signal depending on whether the second error occurs.

10. The electronic device of claim 9 , wherein, when the first voltage is not within a first range, the first monitoring circuit determines that the first error occurs in the bandgap reference circuit, and
wherein, when the second voltage is not within a second range, the second monitoring circuit determines that the second error occurs in the reference buffer.

11. The electronic device of claim 9 , wherein the reference buffer is a first reference buffer, and
wherein the electronic device further comprises:
a second reference buffer configured to generate a third voltage, based on the first voltage; and
a third monitoring circuit configured to determine whether a third error occurs in the second reference buffer based on the third voltage and to determine a logical value of a third alarm signal depending on whether the third error occurs.

12. The electronic device of claim 11 , wherein, when the second error and the third error do not occur in the first reference buffer and the second reference buffer, respectively, the second voltage and the third voltage are equal.

13. The electronic device of c

Assignees

• Samsung Electronics Co Ltd

Inventors

• Yoo Sungmin
• Park Joowon
• Kong Tae-Hwang
• Kim Sangho
• Kim Hyunmyoung
• Lee Jaeseung

Classifications

• G05F3/16 Primary

  being semiconductor devices · CPC title

• G01R31/31721

  Power aspects, e.g. power supplies for test circuits, power saving during test (for scan test G01R31/318575) · CPC title

• G05F1/565

  sensing a condition of the system or its load in addition to means responsive to deviations in the output of the system, e.g. current, voltage, power factor (G05F1/563 takes precedence) · CPC title

• G06F1/3206

  Monitoring of events, devices or parameters that trigger a change in power modality · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title