Compact architecture for multipath low noise amplifier

Patent metadata

Field	Value
Publication number	US-11539334-B2
Application number	US-202117200858-A
Country	US
Kind code	B2
Filing date	Mar 14, 2021
Priority date	Sep 19, 2018
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

Methods and devices used in mobile receiver front end to support multiple paths and multiple frequency bands are described. The presented devices and methods provide benefits of scalability, frequency band agility, as well as size reduction by using one low noise amplifier per simultaneous outputs. Based on the disclosed teachings, variable gain amplification of multiband signals is also presented.

First claim

What is claimed is:

1. A radio frequency (RF) amplifier comprising:
a plurality of first stage amplifiers comprising at least one gain transistor of a first type and an input matching network;
a plurality of second stage amplifiers comprising at least one transistor of a second type with an output matching network; the plurality of second stage amplifiers being connectable to a corresponding plurality of output loads;
a common power supply node coupled to the plurality of first stage amplifier and the second stage amplifier, and
a common ground node coupled to the first stage amplifier and the second stage amplifier,
wherein the RF amplifier has a folded architecture and the RF amplifier is configured to:
receive an input RF signal;
amplify the input RF signal by a combination of a first stage amplifier of the plurality of first stage amplifiers and a second stage amplifier of the plurality of second stage amplifiers to generate an amplified signal; and
feed the amplified signal to an output load at an output RF terminal,

and wherein the RF amplifier is further configured so that two or more output loads are able to receive amplified signals from the first stage amplifier at the same time.

2. The RF amplifier of claim 1 , further comprising a switching module configured to selectively bypass the first stage amplifier and/or the second stage amplifier.

3. The RF amplifier of claim 1 , wherein the first type is N-type metal-oxide-semiconductor (NMOS) and the second type is P-type metal-oxide-semiconductor (PMOS).

4. The RF amplifier of claim 1 , wherein the first stage amplifier and/or the second stage amplifier comprise cascode amplifiers.

5. The RF amplifier of claim 1 , wherein the input matching network and/or the output matching network are a reconfigurable matching network.

6. The RF amplifier of claim 1 , wherein:
the common power supply node is coupled to a voltage source through an RF choke;
the first stage amplifier is biased at a full voltage of the voltage source, and
the second stage amplifier is biased at the full voltage of the voltage source.

7. An integrated circuit comprising a plurality of RF amplifiers of claim 1 .

8. The integrated circuit of claim 7 , wherein the plurality of amplifiers are selectively interconnected to one another.

9. The integrated circuit of claim 8 configured to tune to different frequency bands.

10. The RF amplifier of claim 1 , wherein:
the first stage amplifier further comprises one or more first transistors in a cascode configuration, and a first variable capacitor coupled across gate and source of a first transistor of the one or more first transistors, and
the one or more transistors are coupled to the common power supply node.

11. The RF amplifier of claim 10 , further comprising a first variable inductor coupling the first transistor of the one or more first transistors to the common ground node.

12. The RF amplifier of claim 11 , wherein a combination of the first variable capacitor and the first variable inductor is configured to tune the first stage amplifier to one or more frequency bands.

13. The RF amplifier of claim 12 , wherein the combination of the first variable capacitor and the first variable inductor is further configured to set a desired gain and impedance in correspondence with a desired frequency band of the one or more frequency bands.

14. The RF amplifier of claim 10 , further comprising:
one or more second transistors in a cascode configuration;
a second variable capacitor coupling the second stage amplifier to the output RF terminal, and
a second variable inductor coupling the one or more second transistors to the common ground node.

15. The RF amplifier of claim 14 , wherein a combination of the second variable inductor and the second variable capacitor is configured to tune an input and/or an output of the RF amplifier.

16. The RF amplifier of claim 15 configured to receive bias voltages via gates of the one or more first transistors.

17. The RF amplifier of claim 16 , wherein the one or more first transistors are configured to be in ON or OFF state in correspondence with applied bias voltages.

18. The integrated circuit of claim 7 , wherein each RF amplifier of the plurality of RF amplifiers is configured to tune to a corresponding frequency band of a plurality of frequency bands, each frequency band of the plurality of frequency bands being different from any other frequency band of the plurality of frequency bands.

19. A folded architecture RF amplifier that receives an input RF signal, amplifies the input RF signal, generates an amplified signal, and feeds the amplified signal to an output load at an output RF terminal, the RF amplifier comprising:
a first stage amplifier comprising at least one gain transistor of a first type and an input matching network;
a second stage amplifier comprising at least one transistor of a second type with an output matching network;
a common power supply node coupled to the first stage amplifier and the second stage amplifier;
a common ground node coupled to the first stage amplifier and the second stage amplifier; and
a switching module configured to selectively bypass the first stage amplifier and/or the second stage amplifier;
wherein:
in a first gain state, the switching module is configured to bypass the first stage amplifier, thereby creating a first signal path from the input RF terminal to the output RF terminal through the second stage amplifier;
in a second gain state, the switching module is configured to bypass the second stage amplifier, thereby creating a second signal path from the input RF terminal to the output RF terminal through the first stage amplifier;
in a third gain state, the switching module is configured to bypass the first stage amplifier and the second stage amplifier, thereby creating a third signal path from the input RF terminal to the output RF terminal without amplification, and
in a fourth gain state, the switching module is configured such that neither the first stage amplifier nor the second stage amplifier is bypassed.

20. A method of amplifying a radio frequency signal comprising:
providing a plurality of first stage amplifiers comprising at least one transistor of a first type;
providing a plurality of second stage amplifiers comprising at least one transistor of a second type;
connecting the plurality of second stage amplifier to a corresponding plurality of output loads:
arranging a first stage amplifier of the plurality of first stage amplifiers and a second stage amplifier of the plurality of second stage amplifiers in a folded configuration;
coupling the first stage amplifier and the second stage amplifier to a common power supply node;
coupling the first stage amplifier and the second stage amplifier to a common ground node;
applying an input RF signal to the first stage amplifier to generate an amplified signal at an output of the second stage RF amplifier, and
feeding the amplified signal to two or more output loads to generate corresponding two or more output signals at the same time.

21. The method of claim 20 , wherein the first type the first type is N-type metal-oxide-semiconductor (NMOS) and the second type is P-type metal-oxide-semiconductor (PMOS).

22. The method of claim 20 , further comprising bypassing selectively the first stage amplifier and/or the second stage amplifier to provide more than one amplifier gain.

23. The method of claim 20 ,

Assignees

• Psemi Corp

Inventors

• Klaren Jonathan James

Classifications

• H03F2200/75

  the amplifier stage being a common source configuration MOSFET · CPC title

• H03G5/28

  having semiconductor devices · CPC title

• H03F2200/451

  the amplifier being a radio frequency amplifier · CPC title

• H03F3/195 Primary

  in integrated circuits · CPC title

• H03F2200/297

  the loading circuit of an amplifying stage comprising a capacitor · CPC title