Systems and methods for read error recovery

Patent metadata

Field	Value
Publication number	US-11538547-B2
Application number	US-202017094218-A
Country	US
Kind code	B2
Filing date	Nov 10, 2020
Priority date	Nov 10, 2020
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

Embodiments provide a scheme for determining the order of read threshold voltages used in a read error recovery operation for a memory system. A controller performs one or more read operations on a memory device using one or more read voltages among a plurality of read voltages in a set order. The controller detects a successful read operation among the one or more read operations. The controller determines one or more credits for the one or more read voltages, respectively, in response to the detected successful read operation. The controller updates the set order based on the determined credits.

First claim

What is claimed is:

1. A memory system comprising:
a memory device; and
a controller configured to:
perform one or more read operations on the memory device using one or more read voltages among a plurality of read voltages in a set order;
detect a successful read operation among the one or more read operations;
determine one or more credits for the one or more read voltages, respectively, and in response to the detected successful read operation, incrementally add a value of 1 to an initial credit associated with a read voltage for the detected successful read operation; and
update the set order based on the determined credits,
wherein the plurality of read voltages have respective initial credits, each of which is different.

2. The memory system of claim 1 , wherein the controller is further configured to perform additional read operations on the memory device based on the updated order.

3. The memory system of claim 1 , wherein the controller includes a memory for storing the plurality of read voltages in the set order, each of the plurality of read voltages being stored in association with its determined credit.

4. A memory system comprising:
a memory device; and
a controller configured to:
perform one or more read operations on the memory device using one or more read voltages among a plurality of read voltages in a set order;
detect a successful read operation among the one or more read operations;
determine one or more credits for the one or more read voltages, respectively, in response to the detected successful read operation; and
update the set order based on the determined credits,
wherein the plurality of read voltages have respective initial credits, each of which is different.

5. The memory system of claim 4 , wherein the plurality of read voltages are applied in a first order, and the initial credits are assigned to the plurality of read voltages in a second order such that the higher a read voltage is in the order, the higher its initial credit is.

6. The memory system of claim 5 , wherein the controller increases the initial credit for a successful read voltage by a set value, in response to the successful read operation using the successful read voltage.

7. The memory system of claim 6 , wherein the set value is one, and
wherein the controller:
determines whether the increased credit of the successful read voltage is the same as any of the other initial credits; and
when it is determined that the increased credit is the same as another initial credit of another read voltage, swap the successful read voltage and the another read voltage in the set order to create an updated order.

8. The memory system of claim 6 , wherein the set value is determined based on a credit for the successful read voltage and the highest of the initial credits of the other read voltages, such that the successful read voltage has the highest credit.

9. The memory system of claim 8 , wherein the controller:
determines whether the increased credit is the same as the highest credit; and
when it is determined that the increased credit is the same as the highest credit, reduces each of credits greater than the credit for the successful read voltage by one.

10. The memory system of claim 5 , wherein the controller maintains the multiple initial credits, in response to the successful read operation using the successful read voltage with the highest credit.

11. A method for operating a memory system, which includes a memory device and a controller coupled to the memory device, the method comprising:
performing one or more read operations on the memory device using one or more read voltages among a plurality of read voltages in a set order;
detecting a successful read operation among the one or more read operations;
determining one or more credits for the one or more read voltages, respectively, and in response to the detected successful read operation, incrementally adding a value of 1 to an initial credit associated with a read voltage for the detected successful read operation; and
updating the set order based on the determined credits,
wherein the plurality of read voltages have respective initial credits, each of which is different.

12. The method of claim 11 , further comprising:
performing additional read operations on the memory device based on the updated order.

13. A method for operating a memory system, which includes a memory device and a controller coupled to the memory device, the method comprising:
performing one or more read operations on the memory device using one or more read voltages among a plurality of read voltages in a set order;
detecting a successful read operation among the one or more read operations;
determining one or more credits for the one or more read voltages, respectively, in response to the detected successful read operation; and
updating the set order based on the determined credits,
wherein the plurality of read voltages have respective initial credits, each of which is different.

14. The method of claim 13 , wherein the plurality of read voltages are applied in a first order, and the initial credits are assigned to the plurality of read voltages in a second order such that the higher a read voltage is in the order, the higher its initial credit is.

15. The method of claim 14 , wherein the determining of the credits for the one or more read voltages comprises:
increasing the initial credit for a successful read voltage by a set value, in response to the successful read operation using the successful read voltage.

16. The method of claim 15 , wherein the set value is one;
wherein the determining of the credits for the one or more read voltages comprises: determining whether the increased credit of the successful read voltage is the same as any of the other initial credits; and
wherein the updating of the set order comprises: when it is determined that the increased credit is the same as another initial credit of another read voltage, swapping the successful read voltage and the another read voltage in the set order to create an updated order.

17. The method of claim 15 , wherein the set value is determined based on a credit for the successful read voltage and the highest of the initial credits of the other read voltages, such that the successful read voltage has the highest credit.

18. The method of claim 17 , wherein the determining of the credits for the one or more read voltages comprises:
determining whether the increased credit is the same as the highest credit; and
when it is determined that the increased credit is the same as the highest credit, reducing each of credits greater than the credit for the successful read voltage by one.

19. The method of claim 14 , wherein the determining of the credits for the plurality of read voltages comprises:
maintaining the multiple initial credits, in response to the successful read operation using the successful read voltage with the highest credit.

20. A system comprising:
a memory to store executable instructions for using a plurality of read voltages for one or more read operations on a memory device; and
a control component in communication with the memory to read the executable instructions from the memory to:
perform one or more read operations on the memory device using one or more read voltages among a plurality of read voltages in a set order;
detect a successful read operation among the one or more read operations;
determine one or more credits for the one or more read voltages, re

Assignees

• Sk Hynix Inc

Inventors

• Ren Jingjian
• Lisichenok Alexey
• Kim Jay
• Kim Sungho
• Wong Eric
• Yun Sunmin

Classifications

• G11C29/44 Primary

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/52

  Protection of memory contents; Detection of errors in memory contents · CPC title

• G11C29/12005 Primary

  comprising voltage or current generators · CPC title

• G11C29/18

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title