Architectures for storing and retrieving system data in a non-volatile memory system

Patent metadata

Field	Value
Publication number	US-11538532-B2
Application number	US-202117199383-A
Country	US
Kind code	B2
Filing date	Mar 11, 2021
Priority date	Dec 29, 2020
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

Numerous embodiments are disclosed of improved architectures for storing and retrieving system data in a non-volatile memory system. Using these embodiments, system data is much less likely to become corrupted due to charge loss, charge redistribution, disturb effects, and other phenomena that have caused corruption in prior art non-volatile memory systems.

First claim

What is claimed is:

1. A system, comprising:
an array of non-volatile memory cells arranged into rows and columns;
a sense amplifier to receive current during a read operation from a first non-volatile memory cell in a first column of the array and to indicate a first value stored in the first non-volatile memory cell and to receive current during the read operation from a second non-volatile memory cell in a second column of the array and to indicate a second value stored in the second non-volatile memory cell; and
a logic circuit to receive from the sense amplifier the indicated first value and the indicated second value and to perform an AND operation on the first indicated value and the second indicated value to generate a data bit output based on the indicated first value and the indicated second value.

2. The system of claim 1 , wherein the first non-volatile memory cell and the second non-volatile memory cell are in the same row in the array.

3. The system of claim 1 , wherein the first non-volatile memory cell and the second non-volatile memory cell are in different rows in the array.

4. A system, comprising:
an array of non-volatile memory cells arranged into rows and columns;
a sense amplifier to receive current during a read operation from a first non-volatile memory cell in a first column of the array and to indicate a first value stored in the first non-volatile memory cell and to receive current during the read operation from a second non-volatile memory cell in a second column of the array and to indicate a second value stored in the second non-volatile memory cell; and
a logic circuit to receive from the sense amplifier the indicated first value and the indicated second value and to perform an OR operation on the first indicated value and the second indicated value to generate a data bit output.

5. The system of claim 4 , wherein the first non-volatile memory cell and the second non-volatile memory cell are in the same row in the array.

6. The system of claim 4 , wherein the first non-volatile memory cell and the second non-volatile memory cell are in different rows in the array.

7. A system, comprising:
an array of non-volatile memory cells arranged into rows and columns; and
a sense amplifier to receive combined current during a read operation from a first non-volatile memory cell and a second non-volatile memory cell in a selected column of the array and to generate a data bit output indicating a value based on a comparison of the combined current to a reference current.

Assignees

• Silicon Storage Tech Inc

Inventors

• Liu Xian
• Wang Chunming
• Do Nhan
• Tran Hieu Van

Classifications

• G06F11/1048

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G11C29/74

  using duplex memories, i.e. using dual copies · CPC title

• G11C2029/4402

  Internal storage of test result, quality data, chip identification, repair information · CPC title

• G11C16/26 Primary

  Sensing or reading circuits; Data output circuits · CPC title