Memory controller, memory system including the same, and method of operating the memory controller

Patent metadata

Field	Value
Publication number	US-11537471-B2
Application number	US-202117469377-A
Country	US
Kind code	B2
Filing date	Sep 8, 2021
Priority date	Apr 29, 2019
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A memory controller for controlling a memory operation of a memory device includes: an error correction code (ECC) circuit configured to detect an error of first read data read from the memory device and correct the error; an error type detection logic configured to write first write data to the memory device, compare second read data with the first write data, detect an error bit of the second read data based on a result of the comparing, and output information about an error type identified by the error bit; and a data patterning logic configured to change a bit pattern of input data to reduce an error of the second read data based on the information about the error type.

First claim

What is claimed is:

1. A memory controller for controlling a memory operation of a memory device, the memory controller comprising:
an error correction code (ECC) circuit configured to detect an error bit of first read data read from the memory device and invert the error bit;
an error type detection logic configured to write first write data based on the inverted error bit to the memory device, and output stuck bit information based on second read data which is read the first write data; and
a data patterning logic configured to change a bit pattern of input data which is received from a host based on the stuck bit information and output a second write data.

2. The memory controller of claim 1 , wherein the data patterning logic is further configured to randomize the input data.

3. The memory controller of claim 2 , wherein the data patterning logic is further configured to select a first randomized data among a plurality of a randomized data based on the stuck bit information.

4. The memory controller of claim 3 , wherein data bits of the first randomized data include more data bits corresponding to a stuck bit than data bits of the first write data.

5. The memory controller of claim 1 , wherein data bits of the second write data include at least one of a stuck bit.

6. The memory controller of claim 1 , wherein the first read data is outputted based on a read command.

7. The memory controller of claim 1 , wherein the first read data is configured to a codeword in which data bits and parity bits are combined.

8. The memory controller of claim 1 , if a number of the error bit included in the first read data exceeds a threshold value, wherein the ECC circuit configured to invert the error bit.

9. The memory controller of claim 1 , an error type detection logic further configured to generate the stuck bit information based on a result of performing a plurality of read and/or write operations of the memory device.

10. The memory controller of claim 1 , wherein the memory device includes a phase change random access memory.

11. The memory controller of claim 1 , wherein the memory device includes a three-dimensional (3D) memory cell array.

12. An operating method of a memory system, the operating method comprising:
detecting an error bit of first read data read from a memory device and invert the error bit;
writing first write data based on the inverted error bit to the memory device;
outputting stuck bit information based on second read data which is read the first write data; and
changing a bit pattern of input data which is received from a host based on the stuck bit information and output a second write data.

13. The operating method of claim 12 , further comprising randomizing the input data.

14. The operating method of claim 13 , further comprising selecting a first randomized data among a plurality of a randomized data based on the stuck bit information.

15. The operating method of claim 14 , wherein data bits the first randomized data include more data bits corresponding to a stuck bit than data bits of the first write data.

16. The operating method of claim 13 , wherein data bits of the second write data include at least one of a stuck bit.

17. The operating method of claim 12 , wherein the first read data is outputted based on a read command.

18. The operating method of claim 12 , wherein the first read data is configured to a codeword in which data bits and parity bits are combined.

19. The operating method of claim 12 further comprising, if a number of the error bit included in the first read data exceeds a threshold value, inverting the error bit.

20. The memory controller of claim 12 further comprising generating the stuck bit information based on a result of performing a plurality of read and/or write operations of the memory device.

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Jeongho
• Kim Youngsik
• Baek Seungyou
• Oh Eunchu
• Yoo Youngkwang
• Lee Younggeun

Classifications

• G06F11/1048 Primary

  using arrangements adapted for a specific error detection or correction feature · CPC title

• G06F11/1044 Primary

  with specific ECC/EDC distribution · CPC title

• G06F11/1068

  in sector programmable memories, e.g. flash disk (G06F11/1072 takes precedence) · CPC title

• G06F3/0659

  Command handling arrangements, e.g. command buffers, queues, command scheduling · CPC title

• G06F12/0238

  Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory · CPC title