Control flow mechanism for execution of graphics processor instructions using active channel packing

Patent metadata

Field	Value
Publication number	US-11537403-B2
Application number	US-202117213453-A
Country	US
Kind code	B2
Filing date	Mar 26, 2021
Priority date	Apr 21, 2017
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

An apparatus to facilitate control flow in a graphics processing system is disclosed. The apparatus includes logic a plurality of execution units to execute single instruction, multiple data (SIMD) and flow control logic to detect a diverging control flow in a plurality of SIMD channels and reduce the execution of the control flow to a subset of the SIMD channels.

First claim

What is claimed is:

1. An apparatus comprising:
a graphics processor, including:
a plurality of processing resources to execute pipelined instructions using a plurality of channels; and
flow control circuitry to:
detect that a number of active channels is below a predetermined threshold percentage of the plurality of channels;
detect a diverging control flow impacting a first code region;
responsive to the diverging control flow, trigger recompilation of the first code region;
duplicate, as part of the recompilation, the first code region into a second code region that is smaller than an original size of the first code region and that comprises the number of active channels;
pack an input of the active channels implemented by the second code region;
perform consecutive channel execution on the input of the active channels by executing one active channel at a time; and
unpack an output of the active channels produced by the second code region.

2. The apparatus of claim 1 , wherein the flow control circuitry is to pack input to the active channels into a subset of the plurality of channels responsive to a determination that the number of active channels is below the predetermined threshold percentage.

3. The apparatus of claim 2 , wherein the flow control circuitry is to detect the active channels detects whether the active channels are spread over multiple sections of the plurality of processing resources.

4. The apparatus of claim 3 , wherein the flow control circuitry prevents packing input to the active channels into the subset of the channels upon detecting that the active channels are not spread over the multiple sections.

5. The apparatus of claim 2 , further comprising a register file including:
one or more bit registers; and
one or more byte registers including a plurality of registers.

6. The apparatus of claim 5 , wherein the flow control circuitry is to cause an instruction to locate indices of register bits that are set in a bit register and write the indices to a bytes register.

7. The apparatus of claim 2 , wherein the flow control circuitry is further to unpack output from the subset of the channels into the plurality of channels.

8. The apparatus of claim 1 , wherein the flow control circuitry is to duplicate the first code region within a subset of the plurality of channels.

9. The apparatus of claim 8 , wherein the subset of the channels comprise half of the channels.

10. The apparatus of claim 1 , wherein the graphics processor further comprising profiler circuitry to:
detect shader branch instructions; and
reconfigure hardware resources upon detection of the shader branch instructions.

11. The apparatus of claim 10 , wherein a compiler is to inject instructions into profile branch directions based on statistical sampling.

12. A method comprising:
detecting that a number of active channels is below a predetermined threshold percentage of a plurality of channels of processing resources of a graphics processor;
detecting a diverging control flow impacting a first code region;
responsive to the diverging control flow, triggering recompilation of the first code region;
duplicating, as part of the recompilation, the first code region into a second code region that is smaller than an original size of the first code region and that comprises the number of active channels;
packing an input of the active channels implemented by the second code region;
performing consecutive channel execution on the input of the active channels by executing one active channel at a time; and
unpacking an output of the active channels produced by the second code region.

13. The method of claim 12 , further comprising:
detecting whether the active channels are spread over multiple sections of the processing resources; and
preventing packing input to the active channels into a subset of the channels responsive to detecting that the active channels are not spread over the multiple sections.

14. The method of claim 13 , wherein unpacking the output further comprises unpacking the output from the subset of the channels into the plurality of channels.

15. The method of claim 12 , further comprising:
detecting shader branch instructions; and
reconfiguring hardware resources upon detection of the shader branch instructions.

16. A non-transitory computer readable medium having instructions, which when executed by one or more processors, cause the processors to:
detect that a number of active channels is below a predetermined threshold percentage of a plurality of channels of processing resources of a graphics processor of the one or more processors;
detect a diverging control flow impacting a first code region;
responsive to the diverging control flow, trigger recompilation of the first code region;
duplicate, as part of the recompilation, the first code region into a second code region that is smaller than an original size of the first code region and that comprises the number of active channels;
pack an input of the active channels implemented by the second code region;
perform consecutive channel execution on the input of the active channels by executing one active channel at a time; and
unpack an output of the active channels produced by the second code region.

17. The non-transitory computer readable medium of claim 16 , having instructions, which when executed by the one or more processors, further causes the processors to:
detect whether the active channels are spread over multiple sections of the processing resources; and
prevent packing input to the active channels into a subset of the channels responsive to detecting that the active channels are not spread over the multiple sections.

18. The non-transitory computer readable medium of claim 16 , wherein unpacking the output further comprises unpacking the output from a subset of the channels into the plurality of channels.

19. The non-transitory computer readable medium of claim 16 , having instructions, which when executed by the one or more processors, further causes the processors to:
detect shader branch instructions; and
reconfigure hardware resources upon detection of the shader branch instructions.

20. A system comprising:
a memory; and
a graphics processor communicably couple to the memory, the graphics processor comprising:
a plurality of processing resources to execute pipelined instructions using a plurality of channels; and
flow control circuitry to:
detect that a number of active channels is below a predetermined threshold percentage of the plurality of channels;
detect a diverging control flow impacting a first code region;
responsive to the diverging control flow, trigger recompilation of the first code region;
duplicate, as part of the recompilation, the first code region into a second code region that is smaller than an original size of the first code region and that comprises the number of active channels;
pack an input of the active channels implemented by the second code region;
perform consecutive channel execution on the input of the active channels by executing one active channel at a time; and
unpack an output of the active channels produced by the second code region.

21. The system of claim 20 , wherein the flow control circuitry is to pack input to the active channels into a subset of the plurality of channels responsive to a determination that the number of active channels is below the predetermined threshold percentage.

22. The syste

Assignees

• Intel Corp

Inventors

• Maiyuran Subramaniam M
• Lueh Guei-Yuan
• Pal Supratim
• Chen Gang
• Kommaraju Ananda V
• Chandra Joy
• Koker Altug
• Surti Prasoonkumar
• Puffer David
• Liao Hong Bin
• Ray Joydeep
• Appu Abhishek R
• Shah Ankur N
• Schluessler Travis T
• Kennedy Jonathan
• Burke Devan

Classifications

• G06T1/20 Primary

  Processor architectures; Processor configuration, e.g. pipelining · CPC title

• G06F9/30076

  to perform miscellaneous control operations, e.g. NOP · CPC title

• G06F9/30058

  Conditional branch instructions · CPC title

• G06F9/30036

  Instructions to perform operations on packed data, e.g. vector, tile or matrix operations · CPC title

• G06F9/3887 Primary

  controlled by a single instruction for multiple data lanes [SIMD] · CPC title