Memory devices, systems, and methods for updating firmware with single memory device

Patent metadata

Field	Value
Publication number	US-11537389-B2
Application number	US-202017068492-A
Country	US
Kind code	B2
Filing date	Oct 12, 2020
Priority date	Dec 12, 2017
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A method can include storing first instruction data in a first region of a nonvolatile memory device; mapping addresses of the first region to predetermined memory address spaces of a processor device; executing the first instruction data from the first region with the processor device; receiving second instruction data for the processor device. While the first instruction data remains available to the processor device, the second instruction data can be written into a second region of the nonvolatile memory device. By operation of the processor device, addresses of the second region can be remapped to the predetermined memory address spaces of the processor device; and executing the second instruction data from the second region with the processor device.

First claim

What is claimed is:

1. A method, comprising:
storing first boot instruction data in a first region of a nonvolatile memory device;
by operation of remap circuits in the nonvolatile memory device, mapping addresses of the first region to predetermined memory address spaces of a processor device, the predetermined memory address spaces being accessed in a boot operation of the processor device;
executing the first boot instruction data from the first region with the processor device in the boot operation;
receiving second boot instruction data for the processor device; while the first boot instruction data remains available to the processor device, writing the second boot instruction data into a second region of the nonvolatile memory device;
by operation of the processor device sending data to the nonvolatile memory device, reconfiguring the remap circuits to remapping addresses of the second region to the predetermined memory address spaces of the processor device; and
executing the second boot instruction data from the second region with the processor device in a subsequent boot operation.

2. The method of claim 1 , wherein:
prior to remapping addresses of the second region, the first region occupies a first range of addresses;
the second region occupies a second range of addresses.

3. The method of claim 1 , wherein:
prior to remapping addresses of the second region, the second region is not accessible for read operations.

4. The method of claim 1 , wherein:
the first region and second region of the nonvolatile memory device are different banks of the nonvolatile memory device; wherein accesses to one bank can overlap in time with accesses to other banks.

5. The method of claim 1 , further including:
remapping addresses of the second region to the predetermined memory address spaces of the processor device includes receiving and storing remapping data in at least one configuration register of the nonvolatile memory device.

6. The method of claim 1 , wherein:
the processor device has a memory address space with a predetermined range; and
the second region has an address outside of the predetermined range.

7. The method of claim 1 , wherein:
receiving the second boot instruction data includes receiving the second boot instruction data from a source remote from the nonvolatile memory device and processor device.

8. A memory device, comprising:
at least one memory cell array formed in a substrate arranged into a plurality of separate regions, each region including a plurality of nonvolatile memory cells;
mapping circuits formed in the substrate and configured to map addresses of each region to any one of a plurality of processor address spaces in response to remap data received from a processor device, the processor address spaces including a boot address space from which the processor device accesses in a boot operation;
a configuration store formed in the substrate and coupled to the mapping circuits and configured to store the remap data; and
control circuits formed in the substrate and configured to enable access by the processor device to one region mapped to the boot address space storing one version of processor boot instructions, while writing another version of the processor boot instructions to another region.

9. The memory device of claim 8 , wherein:
the configuration store includes at least one configuration register accessible via a register write operation to the memory device.

10. The memory device of claim 8 , wherein:
the control circuits include an instruction decoder configured to enable access to the configuration store in response to a received instruction.

11. The memory device of claim 8 , wherein:
different remap data change an address decoding of the most significant bits of memory addresses used to access the regions.

12. The memory device of claim 8 , wherein: the regions are different banks of the memory device; wherein accesses to one bank can overlap in time with accesses to other banks.

13. The memory device of claim 8 , wherein:
the mapping circuits are configured to map addresses of each region to a different address space of a processor device.

14. A system, comprising:
a nonvolatile memory (NVM) device including
nonvolatile memory cells arranged into a plurality of regions configured to store at least instruction data, and
mapping circuits configured to assign any of a plurality of different processor memory address ranges to each region in response to remap data;

a processor device is coupled to the NVM device by at least one bus, the processor device configured to
execute boot instruction data in a boot operation by accessing a predetermined processor memory address range that is mapped to a first region of the NVM device by the mapping circuits of the NVM device, and
transmit remap data to the NVM device to reconfigure the mapping circuits of the NVM device to remap the predetermined processor memory address range to a second region of the NVM device that stores updated boot instruction data for execution by the processor device.

15. The system of claim 14 , wherein:
the regions are different banks of the NVM device; wherein
accesses to one bank can overlap in time with accesses to other banks.

16. The system of claim 14 , wherein:
the reconfigured mapping circuits are configured to change an address decoding of the most significant bits of memory addresses used to access the regions in response to the remap data.

17. The system of claim 14 , wherein:
the NVM device and processor device are separated integrated circuits.

18. The system of claim 17 , wherein:
memory arrays of the processor device consist of volatile memory circuits.

19. The system of claim 14 , wherein:
the NVM device is coupled to the processor device by a serial data bus having at least one serial data line on which address and data values are transmitted and received.

20. The system of claim 16 , further including a wireless transceiver configured to receive the updated boot instruction data from a source remote from the nonvolatile memory device and processor device.

Assignees

• Infineon Technolgies LLC
• Infineon Technologies LLC

Inventors

• Rosner Stephan
• Ostrikov Sergey
• Zitlaw Clifford
• Ise Yuichi

Classifications

• G06F2212/1008

  Correctness of operation, e.g. memory ordering · CPC title

• G06F12/0284

  Multiple user address space allocation, e.g. using different base addresses (interprocessor communication G06F15/163) · CPC title

• G06F8/654 Primary

  using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories · CPC title

• G06F9/268

  Microinstruction selection not based on processing results, e.g. interrupt, patch, first cycle store, diagnostic programs · CPC title

• G06F2212/7201

  Logical to physical mapping or translation of blocks or pages · CPC title