Method of manufacturing array substrate, and array substrate

Patent metadata

Field	Value
Publication number	US-11537016-B2
Application number	US-201916964278-A
Country	US
Kind code	B2
Filing date	Dec 13, 2019
Priority date	Feb 2, 2019
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A method of manufacturing an array substrate is provided, which comprises: forming a first metal layer and an insulating layer in sequence on a base substrate, the insulating layer covering the first metal layer; forming an etch barrier layer on the insulating layer; etching the etching barrier layer and the insulating layer multiple times, wherein an effective blocking area of the etching barrier layer decreases successively in each etching to form a connection hole penetrating the insulating layer, the connection hole includes a plurality of via holes connected in sequence, and a slope angle of a hole wall of each via hole is smaller than a preset slope angle; and forming a second metal layer, the second metal layer being connected to the first metal layer through the connection hole.

First claim

What is claimed is:

1. A method of manufacturing an array substrate, comprising:
forming a first metal layer and an insulating layer in sequence on a base substrate, the insulating layer covering the first metal layer;
forming an etching barrier layer on the insulating layer, wherein the etching barrier layer is in contact with the insulating layer;
etching the etching barrier layer and the insulating layer multiple times, wherein an effective blocking area of the etching barrier layer decreases successively in each etching to form a connection hole penetrating the insulating layer, the connection hole includes a plurality of via holes connected in sequence, and a slope angle of a hole wall of each via hole is smaller than a preset slope angle; and
forming a second metal layer, the second metal layer being connected to the first metal layer through the connection hole, wherein
a material of the etching barrier layer is chromium or organosiloxane; and
an etching gas is used in the etching the etching barrier layer and the insulating layer multiple times, wherein an etching selection ratio of the etching gas to the insulating layer and the etching barrier layer is greater than 10:1.

2. The method according to claim 1 , wherein the preset slope angle is greater than 70°, and the slope angle of the hole wall of the via holes is from 50° to 70°.

3. The method according to claim 1 , wherein the step of etching the etching barrier layer and the insulating layer multiple times, to form a connection hole penetrating the insulating layer, comprises:
coating a photoresist on the etching barrier layer;
forming a photoresist hole by a patterning process;
etching, by using a first etching process, the etching barrier layer in the photoresist hole to form a first etched hole;
etching, by using a second etching process, the insulating layer in the first etching hole to form a first transition hole not penetrating the insulating layer;
etching, by using a third etching process, the etching barrier layer to form a second etched hole;
etching, by using a fourth etching process, the second etched hole and the insulating layer in the first transition hole to form the connection hole penetrating the insulating layer;
wherein, the connection hole comprises a first via hole opening to the etching barrier layer and a second via hole communicated with the first via hole and opening to the first metal layer, the slope angle of the hole wall of the second via hole is greater than the slope angle of the hole wall of the first via hole; and
wherein the material of the etching barrier layer is chromium.

4. The method according to claim 3 , wherein the step of forming a second metal layer, comprises:
removing the photoresist remained on the etching barrier layer;
removing the etching barrier layer remained on the insulating layer;
forming the second metal layer on the insulating layer from which the etching barrier layer is removed.

5. The method according to claim 3 , wherein the first etching process is a dry etching process or a wet etching process, and the third etching process is a dry etching process or a wet etching process; wherein, an etching gas used in the dry etching process is O 2 , and an etching solution used in the wet etching process includes ammonium cerium nitrate, glacial acetic acid and water.

6. The method according to claim 3 , wherein the second etching process and the fourth etching process are both dry etching processes, and an etching gas used is a mixed gas of SF 6 and O 2 , or a mixed gas of CF 4 and O 2 .

7. The method according to claim 1 , wherein the step of etching the etching barrier layer and the insulating layer multiple times, to form a connection hole penetrating the insulating layer, comprises:
oxidizing, by using a first mask, the etching barrier layer to obtain a first oxide layer;
etching, by using a fifth etching process, the first oxide layer to form a second transition hole;
oxidizing, by using a second mask, the etching barrier layer to obtain a second oxide layer, an aperture of an opening of the second mask being larger than an aperture of an opening of the first mask;
etching, by using a sixth etching process, the second oxide layer and the insulating layer, to form the connection hole penetrating the insulating layer;
wherein, the connection hole comprises a first via hole opening to the etching barrier layer and a second via hole communicated with the first via hole and opening to the first metal layer, the slope angle of the hole wall of the second via hole is greater than the slope angle of the hole wall of the first via hole.

8. The method according to claim 7 , wherein the step of forming a second metal layer, comprises:
oxidizing the remained etching barrier layer to obtain a third oxide layer; and
forming the second metal layer on the third oxide layer.

9. The method according to claim 7 , wherein material of the etching barrier layer is organosiloxane; the etching barrier layer is oxidized by ultraviolet ray or ozone; the fifth etching process and the sixth etching process are both dry etching processes, and an etching gas used is CF 4 .

10. An array substrate manufactured by using the method according to claim 1 , comprising:
a base substrate;
a first metal layer on the base substrate;
an insulating layer covering the first metal layer, wherein the insulating layer is provided with a connection hole penetrating the insulating layer;
a second metal layer connected to the first metal layer through the connection hole, wherein the connection hole includes a plurality of via holes connected in sequence, and a slope angle of a hole wall of each via hole is less than a preset slope angle and gradually decrease in a direction away from the base substrate.

11. The array substrate according to claim 10 , wherein the preset slope angle is greater than 70°, and the slope angle of the hole wall of the via holes is from 50° to 70°.

12. The array substrate according to claim 10 , wherein the connection hole comprises a first via hole opening to the second metal layer and a second via hole communicated with the first via hole and opening to the first metal layer, the slope angle of the hole wall of the second via hole is greater than the slope angle of the hole wall of the first via hole.

13. The array substrate according to claim 10 , wherein the insulating layer is a multilayer structure, and layers in the multilayer structure that are respectively in contact with the first metal layer and the second metal layer are made of an insulating material.

Assignees

• Hefei Xinsheng Optoelectronics Technology Co Ltd
• Boe Technology Group Co Ltd
• Hefei Xinsheng Optoft Fctronics Tech Co Ltd

Inventors

• Cheng Leilei
• Fang Jingang
• Ding Luke
• Liu Jun
• Li Wei
• Zhou Bin

Classifications

• G02F1/136227 Primary

  Through-hole connection of the pixel electrode to the active element through an insulation layer · CPC title

• G02F1/133345

  Insulating layers (G02F1/1335, G02F1/1337, G02F1/135, G02F1/136 take precedence) · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H10W70/60

  Insulating or insulated package substrates; Interposers; Redistribution layers (leadframes H10W70/40) · CPC title