Array substrate, manufacturing method thereof and display panel

Patent metadata

Field	Value
Publication number	US-10374062-B2
Application number	US-201615519954-A
Country	US
Kind code	B2
Filing date	May 23, 2016
Priority date	Mar 9, 2016
Publication date	Aug 6, 2019
Grant date	Aug 6, 2019

Abstract

The present invention provides an array substrate, a manufacturing method thereof and a display panel. The array substrate includes a substrate and an insulation layer provided on the substrate, the insulation layer including a via therein formed by etching. The insulation layer further includes a plurality of insulation sub-layers stacked on each other, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate under an etching condition for forming the via.

First claim

What is claimed is:

1. An array substrate, comprising a substrate and an insulation layer provided on the substrate, the insulation layer comprising a via therein formed by etching, wherein
the insulation layer comprises a plurality of insulation sub-layers stacked on each other, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate under an etching condition for forming the via;
each of the plurality of insulation sub-layers is a silicon nitride-containing layer; and
an insulation sub-layer which is farther away from the substrate has a smaller ratio of the number of silicon-nitride bonds to that of silicon-hydrogen bonds.

2. The array substrate according to claim 1 , wherein
the insulation layer consists of a first insulation sub-layer and a second insulation sub-layer provided on a side of the first insulation sub-layer far away from the substrate.

3. The array substrate according to claim 2 , wherein
under the etching condition for forming the via, the first insulation sub-layer has an etching rate ranging from 6000 {acute over (Å)}/min to 7000 {acute over (Å)}/min, and the second insulation sub-layer has an etching rate ranging from 8000 {acute over (Å)}/min to 12000 {acute over (Å)}min.

4. The array substrate according to claim 2 , wherein
a ratio of a thickness of the first insulation sub-layer to that of the second insulation sub-layer is equal to or greater than 4:1.

5. The array substrate according to claim 4 , wherein
the thickness of the first insulation sub-layer ranges from 800 {acute over (Å)} to 1700 {acute over (Å)}, and the thickness of the second insulation sub-layer ranges from 200 {acute over (Å)} to 300 {acute over (Å)}.

6. The array substrate according to claim 1 , wherein the insulation layer is a passivation layer, and
the array substrate further comprises a thin film transistor covered by the insulation layer and located on the substrate, and a pixel electrode provided on a side of the insulation layer far away from the substrate, the pixel electrode being connected to a drain of the thin film transistor through the via in the insulation layer.

7. A display panel, comprising an array substrate, which comprises a substrate and an insulation layer provided on the substrate, the insulation layer comprising a via therein formed by etching, wherein
the insulation layer comprises a plurality of insulation sub-layers stacked on each other, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate under an etching condition for forming the via;
each of the plurality of insulation sub-layers is a silicon nitride-containing layer; and
an insulation sub-layer which is farther away from the substrate has a smaller ratio of the number of silicon-nitride bonds to that of silicon-hydrogen bonds.

8. A manufacturing method of an array substrate, comprising steps of
forming a plurality of insulation sub-layers stacked on each other on a substrate sequentially, so that the plurality of insulation sub-layers form an insulation layer, and an insulation sub-layer among the plurality of insulation sub-layers which is farther away from the substrate has a larger etching rate; and
etching the plurality of insulation sub-layers of the insulation layer to form a via, under a same etching condition;
wherein each of the plurality of insulation sub-layers is a silicon nitride-containing layer, and an insulation sub-layer which is farther away from the substrate has a smaller ratio of the number of silicon-nitride bonds to that of silicon-hydrogen bonds.

9. The manufacturing method according to claim 8 , wherein, each of the plurality of insulation sub-layers is formed by a plasma-enhanced chemical vapor deposition process, wherein a mixed gas of silane and ammonia gas is used as a process gas, and the plurality of insulation sub-layers are formed under at least one of the following conditions:
C1: when an insulation sub-layer which is farther away from the substrate is formed, a flow amount of silane, a flow amount of ammonia gas and a ratio of the flow amount of silane to the flow amount of ammonia gas are smaller; and
C2: when an insulation sub-layer which is farther away from the substrate is formed, a radio frequency power of plasma is smaller.

10. The display panel according to claim 7 , wherein
the insulation layer consists of a first insulation sub-layer and a second insulation sub-layer provided on a side of the first insulation sub-layer far away from the substrate.

11. The display panel according to claim 10 , wherein
under the etching condition for forming the via, the first insulation sub-layer has an etching rate ranging from 6000 {acute over (Å)}/min to 7000 {acute over (Å)}/min, and the second insulation sub-layer has an etching rate ranging from 8000 {acute over (Å)}/min to 12000 {acute over (Å)}/min.

12. The display panel according to claim 10 , wherein
a ratio of a thickness of the first insulation sub-layer to that of the second insulation sub-layer is equal to or greater than 4:1.

13. The display panel according to claim 12 , wherein
the thickness of the first insulation sub-layer ranges from 800 {acute over (Å)} to 1700 {acute over (Å)}, and the thickness of the second insulation sub-layer ranges from 200 {acute over (Å)} to 300 {acute over (Å)}.

14. The display panel according to claim 7 , wherein the insulation layer is a passivation layer, and
the array substrate further comprises a thin film transistor covered by the insulation layer and located on the substrate, and a pixel electrode provided on a side of the insulation layer far away from the substrate, the pixel electrode being connected to a drain of the thin film transistor through the via in the insulation layer.

Assignees

• Boe Technology Group Co Ltd
• Ordos Yuansheng Optoelectronics Co Ltd

Inventors

• Sun Yanfei

Classifications

• H10D84/01

  Manufacture or treatment · CPC title

• H10W20/435

  Cross-sectional shapes or dispositions of interconnections · CPC title

• H10W20/082

  the openings being tapered via holes · CPC title

• H10W20/48

  Insulating materials thereof · CPC title

• H01L21/76804

  Electricity · mapped topic