Driver circuit for driving a voltage controlled electro-optical modulator

Patent metadata

Field	Value
Publication number	US-11536990-B2
Application number	US-202117399206-A
Country	US
Kind code	B2
Filing date	Aug 11, 2021
Priority date	Sep 2, 2020
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

Examples include a driver circuit for driving a voltage controlled electro-optical modulator. The driver circuit includes a supply input and an input for receiving the input voltage. The driving circuit further includes a level shifter circuit, which includes first and second capacitors and is electrically connected to the input, and a voltage distribution circuit, which is electrically connected between the level shifter circuit and an output of the driver circuit for providing the output voltage. The level shifter circuit is configured to generate, based on the input voltage and using the first capacitor, a first voltage varying between the positive supply voltage level and a positive first level that is greater than the positive supply voltage level. The level shifter circuit is also configured to generate, based on the input voltage and using the second capacitor, a second voltage varying between ground and a negative second level.

First claim

What is claimed is:

1. A driver circuit comprising:
a level shifter circuit configured to:
generate, based on an input voltage, a first voltage varying between a positive supply voltage level and a positive first level that is greater than the positive supply voltage level, and
generate, based on the input voltage, a second voltage varying between a ground and a negative second level; and

a voltage distribution circuit configured to generate an output voltage that is variable between a positive third level that is equal to or less than the positive supply voltage level and a negative fourth level, wherein an absolute value of the negative fourth level is greater than an absolute value of the positive first level.

2. The driver circuit of claim 1 , wherein the level shifter circuit comprises a capacitor configured to generate the first voltage.

3. The driver circuit of claim 2 , wherein the level shifter circuit comprises a second capacitor configured to generate the second voltage.

4. The driver circuit according to claim 1 , wherein the positive first level is equal to or less than two times the positive supply voltage level.

5. The driver circuit according to claim 1 , wherein an absolute value of the negative second level is equal to or less than the positive supply voltage level.

6. The driver circuit according to claim 1 , wherein an absolute value of the negative fourth level is equal to or less than three times the positive supply voltage level.

7. The driver circuit according to claim 1 , wherein
the level shifter circuit comprises a level shifter up circuit and a level shifter down circuit electrically connected to each other at a first node and a second node;
the level shifter up circuit comprises a first capacitor and is configured to provide the first voltage to the voltage distribution circuit; and
the level shifter down circuit comprises a second capacitor and is configured to provide the second voltage to the voltage distribution circuit.

8. The driver circuit according to claim 7 , wherein
the driver circuit is configured to provide based on the input voltage a control voltage to the first node and an inverted control voltage to the second node, wherein the control voltage varies between the ground and the positive supply voltage level;
the first capacitor is connected via a first NMOS transistor to the positive supply voltage level and is connected to the first node, wherein a gate terminal of the first NMOS transistor is controllable by the second node;
the second capacitor is connected via a first PMOS transistor to the ground and connected to the second node, wherein a first gate terminal of the first PMOS transistor is controllable by the first node.

9. The driver circuit according to claim 8 , wherein
the level shifter up circuit comprises a third capacitor that is connected between the second node and the gate terminal of the first NMOS transistor,
a third node between the third capacitor and the gate terminal of the first NMOS transistor is connected via a second NMOS transistor to the positive supply voltage level,
the gate terminal of the second NMOS transistor is connected to a fourth node between the first NMOS transistor and the first capacitor;
the level shifter down circuit comprises a fourth capacitor that is connected between the first node and the gate terminal of the first PMOS transistor,
a fifth node between the fourth capacitor and the gate terminal of the first PMOS transistor is connected via a second PMOS transistor of the level shifter down circuit to ground, and
the gate terminal of the second PMOS transistor is connected to a sixth node between the first PMOS transistor and the second capacitor.

10. The driver circuit according to claim 9 , wherein the voltage distribution circuit is connected to:
the fourth node between the first NMOS transistor and the first capacitor, wherein at the fourth node the level shifter up circuit is configured to provide the first voltage to the voltage distribution circuit, and
the sixth node between the first PMOS transistor and the second capacitor, wherein at the sixth node the level shifter down circuit is configured to provide the second voltage to the voltage distribution circuit.

11. The driver circuit according to claim 1 , wherein
the voltage distribution circuit comprises a first voltage distribution circuit and a second voltage distribution circuit;
the first voltage distribution circuit is configured to distribute the first voltage such that at a first output terminal a third voltage is variable between ground and the positive first level; and
the second voltage distribution circuit is configured to distribute the second voltage such that at a second output terminal a fourth voltage is variable between the negative second level and the positive third level.

12. The driver circuit according to claim 11 , wherein
the first voltage distribution circuit comprises a third PMOS transistor and a third NMOS transistor;
the third PMOS transistor is configured to provide the first voltage to the first output terminal; and
the third NMOS transistor is configured to provide a conducting path between the first output terminal and the ground, in case the first voltage corresponds to the positive supply voltage level.

13. The driver circuit according to claim 12 , wherein
the first output terminal is connected to a drain terminal of the third PMOS transistor and to a third drain terminal of the third NMOS transistor;
a gate terminal of the third PMOS transistor is connected to a supply input; and
the level shifter circuit is configured to control the gate terminal of the third NMOS transistor based on the input voltage.

14. The driver circuit according to claim 11 , wherein
the second voltage distribution circuit comprises a fourth NMOS transistor and a fourth PMOS transistor;
the fourth NMOS transistor is configured to provide the second voltage to the second output terminal; and
the fourth PMOS transistor is configured to provide a conducting path between the second output terminal and a supply input.

15. The driver circuit according to claim 14 ,
wherein a gate terminal of the fourth NMOS transistor is connected to ground; and
the level shifter circuit is configured to control the gate terminal of the fourth PMOS transistor based on the input voltage, and
wherein
the second output terminal is connected to a drain terminal of the fourth NMOS transistor and to the drain terminal of the fourth PMOS transistor, or
the second output terminal is connected to the drain terminal of the fourth NMOS transistor, to a source terminal of a fifth PMOS transistor of the second voltage distribution circuit and via a fifth NMOS transistor of the second voltage distribution circuit to the drain terminal of the fourth PMOS transistor, wherein the drain terminal and gate terminal of the fifth PMOS transistor are connected to the ground.

16. The driver circuit according to claim 12 ,
wherein
the first voltage distribution circuit comprises a sixth NMOS transistor,
a third drain terminal of the third NMOS transistor is connected via the sixth NMOS transistor to the first output terminal, and
a sixth gate terminal of the sixth NMOS transistor is connected to a supply input; and/or
wherein
the second voltage distribution circuit comprises a sixth PMOS transistor,
a fourth drain terminal of a fourth PMOS transistor is connected via the sixth PMOS transistor, optionally via the sixth PMOS transistor and a fifth NMOS transistor, to the second output terminal, and
the sixth gate termin

Assignees

• Imec Vzw

Inventors

• Guermandi Davide

Classifications

• G02F1/0327

  Operation of the cell; Circuit arrangements (G02F1/05 takes precedence) · CPC title

• H03K3/42

  by the use, as active elements, of opto-electronic devices, i.e. light-emitting and photoelectric devices electrically- or optically-coupled · CPC title

• H03K17/223

  in field-effect transistor switches · CPC title

• G02F1/0123 Primary

  Circuits for the control or stabilisation of the bias voltage, e.g. automatic bias control [ABC] feedback loops · CPC title

• H03K19/018521 Primary

  of complementary type, e.g. CMOS · CPC title