Low input supply and low output impedance charge pump circuit configured for positive and negative voltage generation

Patent metadata

Field	Value
Publication number	US-2022158552-A1
Application number	US-202117494244-A
Country	US
Kind code	A1
Filing date	Oct 5, 2021
Priority date	Nov 19, 2020
Publication date	May 19, 2022
Grant date	—

Abstract

The charge transfer transistors of a positive or negative charge pump are biased at their gate terminals with a control voltage that provides for an higher level of gate-to-source voltage in order to reduce switch resistance in passing a boosted (positive or negative) voltage to a voltage output of the charge pump. This control voltage is generated using a bootstrapping circuit whose polarity of operation (i.e., negative or positive) is opposite to a polarity (i.e., positive or negative) of the charge pump.

First claim

What is claimed is:

1 . A positive charge pump circuit configured to generate an output voltage from an input voltage, wherein a positive voltage level of the output voltage is more positive than a voltage level of the input voltage, comprising:
a negative bootstrapping circuit configured to generate a control signal in response to a first clock signal, wherein the control signal switches between a ground voltage and a negative voltage; a voltage boosting circuit configured to generate a positively boosted voltage in response to a second clock signal; and a charge transfer transistor having a drain terminal coupled to receive said positively boosted voltage and a source terminal coupled to an output node, wherein a gate terminal of the charge transfer transistor is biased by the negative voltage of the control signal to turn on and pass the positively boosted voltage to the output node and generate said output voltage.

2 . The positive charge pump circuit of claim 1 , wherein the first clock signal is a logic inverse of the second clock signal.

3 . The positive charge pump circuit of claim 1 , further comprising a level shifting circuit configured to receive said control signal and generate a level shifted control signal that switches between a level of the positively boosted voltage and said negative voltage, and wherein the level shifted control signal is applied to the gate terminal of the charge transfer transistor.

4 . The positive charge pump circuit of claim 3 , wherein the level shifting circuit comprises a first MOS transistor of a first conductivity type having a source coupled to receive said control signal and a second MOS transistor of a second conductivity type having a source coupled to receive a signal at the level of said positively boosted voltage, wherein a common drain of the first and second MOS transistors is configured to generate said level shifted control signal.

5 . The positive charge pump circuit of claim 4 , wherein the first MOS transistor is gate biased by a first voltage and where the second MOS transistor is gate biased by a second voltage, wherein a level of the second voltage is more positive than a level of the first voltage.

6 . The positive charge pump circuit of claim 1 , wherein the voltage boosting circuit comprises:
a transistor having a source terminal coupled to the input voltage and having a drain terminal where the positively boosted voltage is generated; a capacitor having a first terminal coupled to the drain terminals of said transistor and the charge transfer transistor; and an inverter circuit having an input coupled to receive the second clock signal and an output coupled to a second terminal of the capacitor.

7 . The positive charge pump circuit of claim 1 , wherein the negative bootstrapping circuit comprises:
a transistor having a source terminal coupled to the ground voltage and having a drain terminal where the control signal is generated; a capacitor having a first terminal coupled to the drain terminal of said transistor; and an inverter circuit having an input coupled to receive the first clock signal and an output coupled to a second terminal of the capacitor.

8 . A negative charge pump circuit configured to generate an output voltage from an input voltage, wherein a negative voltage level of the output voltage is more negative than a voltage level of the input voltage, comprising:
a positive bootstrapping circuit configured to generate a control signal in response to a first clock signal, wherein the control signal switches between a first positive voltage and a second positive voltage, wherein a voltage level of the second positive voltage is more positive than a voltage level of the first positive voltage; a voltage boosting circuit configured to generate a negatively boosted voltage in response to a second clock signal; and a charge transfer transistor having a drain terminal coupled to receive said negatively boosted voltage and a source terminal coupled to an output node, wherein a gate terminal of the charge transfer transistor is biased by the second positive voltage of the control signal to turn on and pass the negatively boosted voltage to the output node and generate said output voltage.

9 . The negative charge pump circuit of claim 8 , wherein the first clock signal is a logic inverse of the second clock signal.

10 . The negative charge pump circuit of claim 8 , further comprising a level shifting circuit configured to receive said control signal and generate a level shifted control signal that switches between a level of the negatively boosted voltage and said second positive voltage, and wherein the level shifted control signal is applied to the gate terminal of the charge transfer transistor.

11 . The negative charge pump circuit of claim 10 , wherein the level shifting circuit comprises a first MOS transistor of a first conductivity type having a source coupled to receive said control signal and a second MOS transistor of a second conductivity type having a source coupled to receive a signal at the level of said negatively boosted voltage, wherein a common drain of the first and second MOS transistors is configured to generate said level shifted control signal.

12 . The negative charge pump circuit of claim 11 , wherein the first MOS transistor is gate biased by a first voltage and where the second MOS transistor is gate biased by a second voltage, wherein a level of the first voltage is more positive than a level of the second voltage.

13 . The negative charge pump circuit of claim 8 , wherein the voltage boosting circuit comprises:
a transistor having a source terminal coupled to the input voltage and having a drain terminal where the negatively boosted voltage is generated; a capacitor having a first terminal coupled to the drain terminals of said transistor and the charge transfer transistor; and an inverter circuit having an input coupled to receive the second clock signal and an output coupled to a second terminal of the capacitor.

14 . The negative charge pump circuit of claim 1 , wherein the positive bootstrapping circuit comprises:
a transistor having a source terminal coupled to a positive supply voltage and having a drain terminal where the control signal is generated; a capacitor having a first terminal coupled to the drain terminal of said transistor; and an inverter circuit having an input coupled to receive the first clock signal and an output coupled to a second terminal of the capacitor.

15 . A positive charge pump circuit configured to generate an output voltage from an input voltage, wherein a positive voltage level of the output voltage is more positive than a voltage level of the input voltage, comprising:
a negative bootstrapping circuit configured to generate a first control signal in response to a first clock signal, wherein the first control signal switches between a ground voltage and a negative voltage; a positive bootstrapping circuit configured to generate a second control signal in response to said first clock signal, wherein the second control signal switches between a first positive voltage and a second positive voltage, wherein a voltage level of the second positive voltage is more positive than a voltage level of the first positive voltage; a voltage boosting circuit configured to generate a positively boosted voltage in response to a second clock signal at an intermediate node; a first charge transfer transistor having a drain terminal coupled to said intermediate node and a source terminal coupled to receive the input voltage, wherein a gate terminal of the fi

Assignees

• St Microelectronics Int Nv

Inventors

• Rana Vikas

Classifications

• H02M3/07 Primary

  using capacitors charged and discharged alternately by semiconductor devices with control electrode {, e.g. charge pumps} · CPC title

• H02M3/076

  the clock signals being boosted to a value being higher than the input voltage value · CPC title

• H02M3/071 Primary

  adapted to generate a negative voltage output from a positive voltage source · CPC title

• H02M3/078

  with means for reducing the back bias effect, i.e. the effect which causes the threshold voltage of transistors to increase as more stages are added to the converters · CPC title

• H02M3/075

  including a plurality of stages and two sets of clock signals, one set for the odd and one set for the even numbered stages · CPC title