Semiconductor package structure and method for manufacturing the same

Patent metadata

Field	Value
Publication number	US-11535509-B2
Application number	US-201916685902-A
Country	US
Kind code	B2
Filing date	Nov 15, 2019
Priority date	Nov 15, 2019
Publication date	Dec 27, 2022
Grant date	Dec 27, 2022

Abstract

A semiconductor package structure includes an electronic device having a first surface and an exposed region adjacent to the first surface; a dam disposed on the first surface and surrounding the exposed region of the electronic device; and a filter structure disposed on the dam.

First claim

What is claimed is:

1. A semiconductor package structure, comprising:
an electronic device having a first surface and an exposed region adjacent to the first surface;
a dam disposed on the first surface and surrounding the exposed region of the electronic device;
a filter structure disposed on the dam, wherein the filter structure comprises a first portion and a second portion surrounding the first portion, and
an encapsulant encapsulating the first surface of the electronic device and surrounding the dam,
wherein a surface of the dam is retracted from a top surface of the encapsulant, wherein the encapsulant has a substantially slant surface or a substantially curve surface, and wherein the encapsulant has an extension on the second portion of the filter structure.

2. The semiconductor package structure of claim 1 , wherein the second portion of the filter structure is in direct contact with the dam.

3. The semiconductor package structure of claim 1 , wherein the first portion of the filter comprises a mesh from a top view perspective.

4. The semiconductor package structure of claim 1 , wherein the first portion of the filter structure defines some cylindrical through holes or some cone-shaped through holes.

5. The semiconductor package structure of claim 1 , wherein the second portion of the filter structure has a first thickness adjacent to the first portion of the filter structure and a second thickness away from the first portion of the filter structure, and wherein the first thickness is greater than the second thickness.

6. The semiconductor package structure of claim 1 , wherein the dam has a lower portion having a width greater than an upper portion.

7. The semiconductor package structure of claim 1 , wherein the dam is retracted from a top surface of the encapsulant.

8. The semiconductor package structure of claim 1 , wherein the encapsulant encapsulates the filter structure.

9. The semiconductor package structure of claim 1 , further comprising a conductive wire bonded to the first surface of the electronic device, where an upper surface of the dam is disposed at an elevation equal to or greater than a top portion of the conductive wire.

10. The semiconductor package structure of claim 1 , wherein the dam overlaps or covers the exposed region of the electronic device.

11. The semiconductor package structure of claim 1 , wherein the filter structure has a width less than the electronic device.

12. A semiconductor package structure, comprising:
an encapsulating member having an open cavity defined therein configured to expose an active surface of a semiconductor device;
an filter structure exposed from the open cavity of the encapsulating member, the filter structure including:
a first portion having a plurality of through holes formed therein arranged over the active surface of the semiconductor device, and
a second portion formed around a periphery of the first portion; and

a dam that surrounds the active surface of the semiconductor device and supports the second portion of the filter structure,
wherein the encapsulating member contacts both a lateral surface of the dam and a lateral surface of the filter structure; and
wherein a thickness of the encapsulating member reduces toward an outer edge portion thereof.

13. The structure of claim 12 ,
wherein in a lateral cross section of the filter structure that shows both of the second portions supported on the dam, the second portions of the filter structure have asymmetric thickness profiles.

Assignees

• Advanced Semiconductor Eng

Inventors

• Liu wei-wei
• Wong Huei-Siang
• Lai Lu-Ming

Classifications

• B81C2201/0132

  Dry etching, i.e. plasma etching, barrel etching, reactive ion etching [RIE], sputter etching or ion milling · CPC title

• B81B2201/10

  Microfilters, e.g. for gas or fluids · CPC title

• G01N33/004

  CO or CO2 · CPC title

• B81B2201/0214

  Biosensors; Chemical sensors · CPC title

• B81B2207/098

  Arrangements not provided for in groups B81B2207/092 - B81B2207/097 · CPC title