Antenna apparatus and method

Patent metadata

Field	Value
Publication number	US-11532868-B2
Application number	US-202016826538-A
Country	US
Kind code	B2
Filing date	Mar 23, 2020
Priority date	Dec 13, 2012
Publication date	Dec 20, 2022
Grant date	Dec 20, 2022

Abstract

An antenna apparatus comprises a semiconductor die in a molding compound layer, a first through via is between a sidewall of the semiconductor die and a sidewall of the molding compound layer and an antenna structure over the molding compound layer, wherein a first portion of the antenna structure is directly over a top surface of the semiconductor die and a second portion of the antenna structure is directly over a top surface of the first through via.

First claim

What is claimed is:

1. A semiconductor device comprising:
a semiconductor die;
a molding compound extending along sidewalls of the semiconductor die;
a through via extending from a first side of the molding compound to a second side of the molding compound;
a first redistribution structure on the first side of the molding compound; and
a second redistribution structure on the second side of the molding compound, wherein the second redistribution structure comprises an antenna structure, wherein a signal transmission path between the semiconductor die and the antenna structure is entirely within the second redistribution structure.

2. The semiconductor device of claim 1 , wherein the antenna structure extends only partially over the through via.

3. The semiconductor device of claim 1 , wherein the antenna structure extends completely over the through via.

4. The semiconductor device of claim 1 , wherein the antenna structure comprises a first metal line and a second metal line, the first metal line extending laterally away from the semiconductor die in a first direction, the second metal line extending laterally away from the semiconductor die in a second direction opposite to the first direction.

5. The semiconductor device of claim 1 , wherein the first redistribution structure comprises an external connector.

6. The semiconductor device of claim 1 , wherein the second redistribution structure is free of an external connector.

7. The semiconductor device of claim 6 , wherein the external connector comprises a solder connection.

8. A semiconductor device comprising:
a semiconductor die having a plurality of conductive contacts;
a molding compound extending along sidewalls of the semiconductor die;
through vias extending from a first side of the molding compound to a second side of the molding compound;
a plurality of first dielectric layers on the first side of the molding compound;
a plurality of first conductive features in the plurality of first dielectric layers, the plurality of first conductive features being electrically interposed between corresponding ones of the through vias and conductive contacts of the semiconductor die; and
an antenna in the plurality of first dielectric layers, wherein the antenna is only directly electrically connected to the semiconductor die.

9. The semiconductor device of claim 8 , wherein the antenna comprises a first metal line and a second metal line, the first metal line extending away from a first side of the semiconductor die, the second metal line extending away from a second side of the semiconductor die.

10. The semiconductor device of claim 9 , wherein the first side is an opposite side from the second side.

11. The semiconductor device of claim 8 , wherein the antenna completely covers at least one through via of the through vias in a plan view.

12. The semiconductor device of claim 8 , wherein the antenna only partially overlaps at least one through via of the through vias in a plan view.

13. The semiconductor device of claim 8 further comprising external connectors, wherein the through vias are electrically interposed between the external connectors and the semiconductor die.

14. The semiconductor device of claim 8 , wherein at least one of the first plurality of dielectric layers covers the antenna.

15. A semiconductor device comprising:
a semiconductor die;
a molding compound extending along sidewalls of the semiconductor die;
through vias extending through the molding compound;
a plurality of first dielectric layers on a first side of the molding compound;
a plurality of second dielectric layers on a second side of the molding compound, the first side of the molding compound being opposite the second side of the molding compound;
a plurality of first conductive paths in the plurality of first dielectric layers, the plurality of first conductive paths being electrically interposed between corresponding ones of the through vias and the semiconductor die;
an antenna in the first plurality of dielectric layers; and
one or more second conductive paths in the plurality of first dielectric layers, the one or more second conductive paths being electrically interposed between the antenna and the semiconductor die, the one or more second conductive paths being electrically isolated from the through vias by the plurality of first dielectric layers.

16. The semiconductor device of claim 15 , wherein the one or more second conductive paths extend higher above the semiconductor die than the plurality of first conductive paths.

17. The semiconductor device of claim 15 further comprising backside interconnects in the plurality of second dielectric layers, wherein the through vias are electrically interposed between the semiconductor die and the backside interconnects.

18. The semiconductor device of claim 15 , wherein the one or more second conductive paths extend laterally over the molding compound.

19. The semiconductor device of claim 15 , wherein the antenna extends at least partially over the semiconductor die and at least a first through via of the through vias.

20. The semiconductor device of claim 19 , wherein the antenna extends completely over at least a second through via of the through vias.

Assignees

• Taiwan Semiconductor Mfg Co Ltd

Inventors

• Chih Lai Wei
• Liu Monsen
• Yeh En-Hsiang
• Wang Chuei-Tang
• Yu Chen-Hua

Classifications

• H10W74/114

  by a substrate and the encapsulations · CPC title

• H10W74/019

  using temporary auxiliary substrates (H10W74/017 takes precedence) · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W72/9413

  on encapsulations · CPC title

• H10W72/874

  On different surfaces · CPC title