Semiconductor packages with indications of die-specific information

Patent metadata

Field	Value
Publication number	US-11532490-B2
Application number	US-201916548084-A
Country	US
Kind code	B2
Filing date	Aug 22, 2019
Priority date	Aug 22, 2019
Publication date	Dec 20, 2022
Grant date	Dec 20, 2022

Abstract

Semiconductor device packages and associated methods are disclosed herein. In some embodiments, the semiconductor device package includes (1) a first surface and a second surface opposite the first surface; (2) a semiconductor die positioned between the first and second surfaces; and (3) an indication positioned in a designated area of the first surface. The indication includes a code presenting information for operating the semiconductor die. The code is configured to be read by an indication scanner coupled to a controller.

First claim

I claim:

1. A semiconductor device package, comprising:
a first surface and a second surface opposite the first surface;
a semiconductor die between the first and second surfaces;
a first indication at a designated area of the first surface, the first indication including a first code presenting information for operating the semiconductor die, the first code being configured to be read by an indication scanner; and
a security indication on the first surface, the security indication including a security code presenting a key for decoding the information for operating the semiconductor die,
wherein the information for operating the semiconductor die includes one or more parameters that include an address for redundancy.

2. The semiconductor device package of claim 1 , wherein the semiconductor device package further comprises a second indication including a second code presenting the information for operating the semiconductor die.

3. The semiconductor device package of claim 2 , wherein the second indication is positioned in the designated area of the first surface.

4. The semiconductor device package of claim 2 , wherein the designated area is a first designated area, and wherein the second indication is positioned in a second designated area of the first surface.

5. The semiconductor device package of claim 2 , wherein the designated area is a first designated area, and wherein the second indication is positioned in a second designated area of the second surface.

6. The semiconductor device package of claim 1 , wherein the semiconductor device package does not include a fuse.

7. The semiconductor device package of claim 2 , wherein the first code includes a QR code, and wherein the second code includes a barcode.

8. The semiconductor device package of claim 1 , further comprising a configuration latch configured to receive the information for operating the semiconductor die during a power-on process of the semiconductor device package.

9. The semiconductor device package of claim 2 , wherein the indication scanner is a first indication scanner, and wherein the second code is configured to be read by a second indication scanner.

10. The semiconductor device package of claim 1 , wherein the information for operating the semiconductor die is a first set of information for operating the semiconductor die, and wherein the semiconductor device package further comprises a second indication including a second code presenting a second set of information for operating the semiconductor die.

11. The semiconductor device package of claim 10 , wherein the second set of information is generally the same as the first set of information.

12. The semiconductor device package of claim 10 , wherein the first set of information includes a first set of parameters for operating the semiconductor die, and wherein the second set of information includes a second set of parameters for operating the semiconductor die.

13. The semiconductor device package of claim 1 , wherein the information for operating the semiconductor die includes a testing result of the semiconductor die.

14. A method of providing information associated with a semiconductor die, comprising:
positioning the semiconductor die in a semiconductor device package, the semiconductor device package having a first surface;
determining a designated area on the first surface;
forming a first indication in the designated area, the first indication including a first code presenting information for operating the semiconductor die, the first code being configured to be read by an indication scanner; and
forming a security indication on the first surface including a security code presenting a key for decoding the information for operating the semiconductor die,
wherein the information for operating the semiconductor die includes one or more parameters that include an address for redundancy.

15. The method of claim 14 , wherein the method further comprises forming a second indication including a second code presenting the information for operating the semiconductor die.

16. The method of claim 15 , wherein the designated area is a first designated area, and wherein the method further comprises:
determining a second designated area on the first surface; and
forming the second indication in the second designated area.

17. The method of claim 15 , wherein the designated area is a first designated area, and wherein the method further comprises:
determining a second designated area on a side surface of the semiconductor device package; and
forming the second indication in the second designated area.

Assignees

• Micron Technology Inc

Inventors

• Pio Federico

Classifications

• H10P72/06

  Apparatus for monitoring, sorting, marking, testing or measuring · CPC title

• H10P54/00

  Cutting or separating of wafers, substrates or parts of devices · CPC title

• H10W46/401

  for identification or tracking · CPC title

• H10W46/201

  located on the periphery of wafers, e.g. orientation notches or lot numbers · CPC title

• H10W46/106

  digital information, e.g. bar codes · CPC title