Power electronics assemblies with CIO bonding layers and double sided cooling, and vehicles incorporating the same

Patent metadata

Field	Value
Publication number	US-11527458-B2
Application number	US-201916569762-A
Country	US
Kind code	B2
Filing date	Sep 13, 2019
Priority date	Jan 30, 2018
Publication date	Dec 13, 2022
Grant date	Dec 13, 2022

Abstract

A 2-in-1 power electronics assembly includes a frame with a lower dielectric layer, an upper dielectric layer spaced apart from the lower dielectric layer, and a sidewall disposed between and coupled to the lower dielectric layer and the upper dielectric layer. The lower dielectric layer includes a lower cooling fluid inlet and the upper dielectric layer includes an upper cooling fluid outlet. A first semiconductor device assembly and a second semiconductor device assembly are included and disposed within the frame. The first semiconductor device is disposed between a first lower metal inverse opal (MIO) layer and a first upper MIO layer, and the second semiconductor device is disposed between a second lower MIO layer and a second upper MIO layer. An internal cooling structure that includes the MIO layers provides double sided cooling for the first semiconductor device and the second semiconductor device.

First claim

What is claimed is:

1. An electronic assembly comprising:
a lower dielectric layer;
an upper dielectric layer;
a lower MIO layer;
an upper MIO layer, wherein an upper fluid chamber and a lower fluid chamber are defined by the lower dielectric layer, the upper dielectric layer, the lower MIO layer and the upper MIO layer; and
a semiconductor device, wherein:
a lower surface of the semiconductor device is bonded to an upper surface of the lower MIO layer; and
an upper surface of the semiconductor device is bonded to a lower surface of the upper MIO layer.

2. The electronic assembly of claim 1 , further comprising an isolating MIO layer, wherein the isolating MIO layer is spaced apart from the lower MIO layer.

3. The electronic assembly of claim 2 , wherein the isolating MIO layer is bonded to the lower surface of the semiconductor device.

4. The electronic assembly of claim 1 , further comprising an isolating MIO layer, wherein the isolating MIO layer is spaced apart from the upper MIO layer.

5. The electronic assembly of claim 4 , wherein the isolating MIO layer is bonded to the upper surface of the semiconductor device.

6. The electronic assembly of claim 1 , wherein:
the lower MIO layer is bonded to the lower dielectric layer; and
the upper MIO layer is bonded to the upper dielectric layer.

7. The electronic assembly of claim 6 , further comprising a first electrode, wherein the first electrode is disposed between the upper dielectric layer and the upper MIO layer.

8. The electronic assembly of claim 7 , further comprising a second electrode, wherein the second electrode is disposed between the lower dielectric layer and the lower MIO layer.

9. The electronic assembly of claim 6 , wherein the semiconductor device and the upper MIO layer are bonded to a middle dielectric layer.

10. An electronic assembly comprising:
a lower dielectric layer;
an upper dielectric layer;
a lower MIO layer;
an upper MIO layer; and
a semiconductor device, wherein:
the lower MIO layer is bonded to the lower dielectric layer;
the upper MIO layer is bonded to the upper dielectric layer;
an upper fluid chamber and a lower fluid chamber are defined by the lower dielectric layer, the upper dielectric layer, the lower MIO layer and the upper MIO layer;
a lower surface of the semiconductor device is bonded to an upper surface of the lower MIO layer; and
an upper surface of the semiconductor device is bonded to a lower surface of the upper MIO layer.

11. The electronic assembly of claim 10 , further comprising an isolating MIO layer, wherein the isolating MIO layer is spaced apart from the lower MIO layer.

12. The electronic assembly of claim 11 , wherein the isolating MIO layer is bonded to the lower surface of the semiconductor device.

13. The electronic assembly of claim 10 , further comprising an isolating MIO layer, wherein the isolating MIO layer is spaced apart from the upper MIO layer.

14. The electronic assembly of claim 13 , wherein the isolating MIO layer is bonded to the upper surface of the semiconductor device.

15. The electronic assembly of claim 10 , further comprising a first electrode, wherein the first electrode is disposed between the upper dielectric layer and the upper MIO layer.

16. The electronic assembly of claim 15 , further comprising a second electrode, wherein the second electrode is disposed between the lower dielectric layer and the lower MIO layer.

17. The electronic assembly of claim 10 , further comprising a middle dielectric layer, wherein the semiconductor device and the upper MIO layer are bonded to the middle dielectric layer.

18. An electronic assembly comprising:
a first semiconductor assembly comprising a first lower MIO layer, a first upper MIO layer, and a first semiconductor device; and
a second semiconductor assembly comprising a second lower MIO layer, a second upper MIO layer, and a second semiconductor device;
a lower dielectric layer;
an upper dielectric layer;
an upper fluid chamber between the first semiconductor assembly and the second semiconductor assembly; and
a lower fluid chamber between the first semiconductor assembly and the second semiconductor assembly,
wherein:
the upper fluid chamber and the lower fluid chamber are defined by the lower dielectric layer, the upper dielectric layer, the first lower MIO layer and the first upper MIO layer;
a lower surface of the first semiconductor device is bonded to an upper surface of the first lower MIO layer;
an upper surface of the first semiconductor device is bonded to a lower surface of the first upper MIO layer;
a lower surface of the second semiconductor device is bonded to an upper surface of the second lower MIO layer; and
an upper surface of the second semiconductor device is bonded to a lower surface of the second upper MIO layer.

Assignees

• Toyota Eng & Mfg North America

Inventors

• Dede Ercan Mehmet
• Joshi Shailesh N

Classifications

• H10W99/00

  Subject matter not provided for in other groups of this subclass · CPC title

• H10W95/00

  Packaging processes not covered by the other groups of this subclass · CPC title

• H10W90/401

  characterised by multiple insulating or insulated package substrates, interposers or RDLs · CPC title

• H10W76/45

  Liquid fillings · CPC title

• H10W70/614

  the multiple chips being integrally enclosed · CPC title