High-speed communication link with self-aligned scrambling

Patent metadata

Field	Value
Publication number	US-11522738-B1
Application number	US-202117354332-A
Country	US
Kind code	B1
Filing date	Jun 22, 2021
Priority date	Jun 22, 2021
Publication date	Dec 6, 2022
Grant date	Dec 6, 2022

Abstract

High-speed communication links with self-aligned scrambling on a communication link that sends scrambled signals may include a slave device that may self-align by initially detecting an unscrambled preamble symbol and more particularly detect an edge of the unscrambled preamble symbol. Based on the detected edge, a fine alignment adjustment may be made by testing subsequent scrambled data for a repeated pattern such as an IDLE symbol by comparing the repeated pattern to a candidate scrambled sequence that has been received through the communication link. The comparison may use an exclusive OR (XOR) circuit on some bits to derive a scrambler seed that is used to test for a match for the remaining bits. If there is a match, the scrambler seed and frame alignment have been detected and alignment is achieved.

First claim

What is claimed is:

1. A device comprising:
a physical layer (PHY) configured to be coupled to a communication link and receive signals therefrom;
an alignment circuit coupled to the PHY, the alignment circuit comprising an exclusive OR (XOR) circuit; and
a control circuit configured to:
cause the alignment circuit to detect a possible edge of an unscrambled preamble symbol in an alignment portion of a received signal;
based on a position of the possible edge, check a scrambled known symbol for a scrambler seed and alignment; and
align based on checking the scrambled known symbol;

wherein the XOR circuit is configured to perform an XOR operation on a portion of the received signal at the possible edge with an unscrambled version of the scrambled known symbol.

2. The device of claim 1 , wherein the device comprises a transceiver integrated circuit (IC).

3. The device of claim 1 , wherein the PHY comprises a universal serial bus (USB) PHY.

4. The device of claim 1 , wherein the PHY comprises a peripheral component interconnect express (PCIE) PHY.

5. The device of claim 1 , wherein the PHY comprises a DIGRF PHY.

6. The device of claim 1 , wherein the PHY comprises a QLINK PHY.

7. The device of claim 1 , wherein the PHY comprises a high-speed serial PHY.

8. The device of claim 1 , wherein the alignment circuit is configured to determine a possible scrambler seed based on the XOR operation on the portion of the received signal at the possible edge with the unscrambled version of the scrambled known symbol.

9. The device of claim 8 , wherein the alignment circuit is configured to test the possible scrambler seed using a second portion of the received signal.

10. The device of claim 1 , wherein the control circuit is further configured to receive the received signal through the PHY and the received signal comprises the alignment portion, a transport portion, and an enter sleep portion.

11. The device of claim 1 , wherein the received signal comprises the alignment portion and the alignment portion comprises:
a preamble portion containing the unscrambled preamble symbol; and
a scrambled portion containing the scrambled known symbol.

12. The device of claim 11 , wherein the preamble portion containing the unscrambled preamble symbol contains a plurality of unscrambled preamble symbols.

13. The device of claim 11 , wherein the scrambled portion containing the scrambled known symbol contains a plurality of scrambled known symbols.

14. The device of claim 11 , wherein the control circuit is configured to be in a sleep mode prior to receipt of the received signal.

15. A host comprising:
a physical layer (PHY) configured to be coupled to a communication link and send signals thereon;
a scrambler circuit; and
a control circuit configured to:
assemble a signal using a plurality of unscrambled preamble symbols followed by a second plurality of scrambled known symbols using the scrambler circuit, wherein a preamble symbol in the plurality of unscrambled preamble symbols is sixteen (16) bits; and
send the signal to a device over the communication link through the PHY.

16. The host of claim 15 , wherein the host comprises a modem.

17. The host of claim 15 , wherein the PHY comprises a high-speed serial PHY.

18. The host of claim 15 , wherein the scrambler circuit has a width of twenty-three (23) bits.

19. The host of claim 15 , wherein a preamble symbol in the plurality of unscrambled preamble symbols is 1111_1111_0000_0000.

20. The host of claim 15 , wherein a known symbol in the second plurality of scrambled known symbols is forty (40) bits.

21. A computing device comprising:
a serial communication link;
a host comprising:
a host physical layer (PHY) coupled to the serial communication link and configured to send signals thereon;
a scrambler circuit; and
a control circuit configured to:
assemble a signal using a plurality of unscrambled preamble symbols followed by a second plurality of scrambled known symbols using the scrambler circuit; and
send the signal to a device over the serial communication link through the host PHY; and

a device comprising:
a device PHY coupled to the serial communication link and configured to receive the signal therefrom;

an alignment circuit coupled to the device PHY, the alignment circuit comprising an exclusive OR (XOR) circuit; and
a control circuit configured to:
cause the alignment circuit to detect a possible edge of an unscrambled preamble symbol in an alignment portion of a received signal;
based on a position of the possible edge, check a scrambled known symbol for a scrambler seed and alignment; and
align based on checking the scrambled known symbol;

wherein the XOR circuit is configured to perform an XOR operation on a portion of the received signal at the possible edge with an unscrambled version of the scrambled known symbol.

22. The computing device of claim 21 , wherein the serial communication link comprises a QLINK bus.

23. A method for aligning a device coupled to a communication link, the method comprising:
receiving a plurality of unscrambled preamble symbols;
detecting an edge of one of the plurality of unscrambled preamble symbols;
based on the edge, testing, using an alignment circuit comprising an exclusive OR (XOR) circuit, a scrambled known symbol against an unscrambled version of the scrambled known symbol to derive a scrambler seed; and
testing a portion of the scrambled known symbol using the scrambler seed.

24. The method of claim 23 , further comprising receiving a plurality of scrambled known symbols after receiving the plurality of unscrambled preamble symbols.

25. The method of claim 24 , further comprising receiving a transport portion of a signal after receiving the plurality of scrambled known symbols.

26. The method of claim 23 , further comprising waking from a sleep mode before receiving the plurality of unscrambled preamble symbols.

27. The method of claim 23 , wherein receiving the plurality of unscrambled preamble symbols comprises receiving a symbol having sixteen (16) bits.

28. The method of claim 27 , wherein receiving the symbol having 16 bits comprises receiving a symbol comprising 1111_1111_0000_0000.

Assignees

• Qualcomm Inc

Inventors

• Ben-Chen Tomer Rafael
• Graif Sharon
• Amarilio Lior

Classifications

• H04L2007/045

  Fill bit or bits, idle words · CPC title

• H04W72/0466

  the resource being a scrambling code · CPC title

• H04L25/49 Primary

  using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels {; Baseband coding techniques specific to data transmission systems (spectral shaping H04L25/03828)} · CPC title

• H04L25/03866 Primary

  using scrambling · CPC title

• H03K19/215

  using field-effect transistors · CPC title